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Forum: FPGA, VHDL & Verilog Translate on and Translate off


Translate on and Translate off
von Aymen K. (aymen)

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Hi all,

What is this constraint:


Translate on and Translate off: the Verilog code between Translate on 
and Translate off is ignored for synthesis.

Thank you

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Re: Translate on and Translate off
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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What is unclear with this statement?
"synthesis" means "implementaion to real hardware"

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