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Forum: FPGA, VHDL & Verilog There are no HDL sources in file set 'sources_1'. Please use the Add Sources command.


Author: Rohan Narkhede (Guest)
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Hi,

I am getting an error : There are no HDL sources in file set 
'sources_1'. Please use the Add Sources command.

The code file and the error screenshot are attached. Please let me know 
what could be the cause of error and how to remove it.

Thanks and regards,
Rohan Narkhede

Author: Rohan Narkhede (Guest)
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Just to add, I am using Xilinx Vivado for code compilation.

Author: Rainer (Guest)
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The screenshot shows syntax error. You have to fix them first.

Author: Rainer (Guest)
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What does vivado complain about. If you click on the "syntax error 
files" you should see in which line your problem is.

Author: Rohan Narkhede (Guest)
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Hi,

The syntax error it shows is at line 42 and 44. (Please see the new 
screenshot attached with this reply). I don't understand what is the 
syntax error here, as I have ended the process and ended the 
architecture - reg_arch like normal syntax.

Thanks an dregards,
Rohan Narkhede

Author: derLars (Guest)
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There is an "end if;" missing right in front of end process!

Author: Rohan Narkhede (Guest)
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Thank you so much derLars!!

Author: derLars (Guest)
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If you use tabs consequently, it is very easy to observe, like:

entity reg is
  port(
    clk     : in  std_logic;
    ...
    reset   : in  std_logic
  );
end entity reg;

architecture reg_arch of reg is
  signal r_reg : std_logic_vector(1 downto 0);
  ...
begin
  process(clk)
  begin
    if reset = '1' then
    ...
    elsif rising_edge(clk) then
      if ctrl0 = '0' ... then
      ...
      elsif ...
      ...
      elsif ...
      ...
      end if;
      <<<<<<<<<<<<<<<<<<< here is something obviously missing!
  end process;

  dout <= r_reg;
  
end architecture;


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