Sorry , am pure noob with the Verilog I need to create register and he should read and store four 10 bit numbers, under the control of a clock signal – the output should be a single 10‐bit number that is the average of the four numbers stored. could you tell me what I am doing wrong or correct my code? module average(a1,b,clk,c); input [9:0] a1; input clk,b; output [9:0]c; reg [9:0] in1,in2,in3,in4,avg; reg [11:2] Sum; always @ (a1,posedge clk); begin in1=a1;in2=in1;in3=in2;in4=in3; in1+in2+in3+in4=Sum; Sum/4=average end endmodule
Guest wrote: > could you tell me what I am doing wrong or correct my code? What do you get with that code? And what did you expect instead? If c is your output, why do you never assign a value to it? What error do you get for this line here:
1 | in1+in2+in3+in4=Sum; |
Shouldn't you change the operands of the equals sign?
Lothar M. wrote: > What do you get with that code it showing me error near begin expecting endmodule module average(a1,b,clk,c); c must be the average of 4 numbers
Guest wrote: > it showing me error near begin expecting endmodule > module average(a1,b,clk,c); And now? Why not having a look at other Verilog code? I'm usually doing VHDL, but afdter a short search with Google I would say: get rid of the ";" at the end of that line! And also you should have a look at the assginments "=" vs "<=" (blocking vs. non blocking). As far as I see you should use the second one for in1..4 to get the desired register set... http://www.asic-world.com/tidbits/blocking.html
hi, thanks for first help but now I stuck with the reset button How I can perform it here? module averager (data_in,AVG,clk); input clk; input[9:0]data_in; output[11:2] AVG; reg [9:0] data[3:0]; reg [11:2] avg_reg; always @ (posedge clk) begin data[0]<=data[1]; data[1]<=data[2]; data[2]<=data[3]; data[3]<=data_in; avg_reg<= data[0] + data[1] + data[2] + data[3]; end assign AVG = avg_reg [11:2]; endmodule
I introduced an asynchronous reset signal. I'm not simulating this code. You can try. module averager (data_in,AVG,clk,rst); input clk,rst; input[9:0]data_in; output[11:2] AVG; reg [9:0] data[3:0]; reg [11:2] avg_reg; always @ (posedge clk or posedge rst) begin if(rst) begin data[0]<=0; data[1]<=0; data[2]<=0; data[3]<=0; avg_reg<=0; end else begin data[0]<=data[1]; data[1]<=data[2]; data[2]<=data[3]; data[3]<=data_in; avg_reg<= data[0] + data[1] + data[2] + data[3]; end end assign AVG = avg_reg [11:2]; endmodule
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