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Forum: FPGA, VHDL & Verilog question to generics and ports


question to generics and ports
von Andreas F. (parafux)

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how can is specify with generics how many ports i want and the width of 
each vector port?

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Re: question to generics and ports
von Vipin L. (lal87)

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Look at this example,
http://vhdlguru.blogspot.in/2010/03/generics-in-vhdl-construction-of.html

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Re: question to generics and ports
von Fred (Guest)

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For defining the number of ports and not only the width of each port, I 
would recommend using an array, which is defined within a package

within the Package:
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type tIoArray is array (gNumber -1 downto 0) of std_logic_vector (gWidth - 1 downto 0);


within the entity:
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entity myEnt is

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port(

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  myInput : in tIoArray;

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  ...

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);

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