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Forum: FPGA, VHDL & Verilog question to generics and ports


Author: Andreas Felber (parafux)
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how can is specify with generics how many ports i want and the width of 
each vector port?

Author: Vipin Lal (lal87)
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Author: Fred (Guest)
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For defining the number of ports and not only the width of each port, I 
would recommend using an array, which is defined within a package

within the Package:
type tIoArray is array (gNumber -1 downto 0) of std_logic_vector (gWidth - 1 downto 0);

within the entity:
entity myEnt is
port(
  myInput : in tIoArray;
  ...
);

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