Hi all, so I am a newbie in the feild of verilog and HDL design. I inherited a very large Quartus project which I am trying to make sense of.I am essentially an embedded c programmer and used to the function calls and ability to search for variables and functions and decode the flow. Can someone tell me how to go about decoding this project.is there any software that can help me. In quartus i cant even find a search entire project feature.So figuring out where some of the signals are coming from, i.e the source of input for some of the modules is daunting to me :( Please help out.
large project- understnd /decode wrote: > I inherited a very large Quartus project which I am trying to make > sense of. Why that? Because you must find some "random" and "obscure" problems within? Or is it running fine, but you must maintain this project further on? If the second: did you already "play araound" with Verilog and simple designs like a blinking led, a chasing light, a RS232 interface or similar simple things? If the first: go and get a pro. There will be some asynchronous parts inside the design which you will not be able find (at least for the next 2 years)... > I am essentially an embedded c programmer Huh, thats a major drawback. FORGET all the "software thinking". Verilog is a HDL (= Hardware DESCRIPTION Language). And to describe something you must have a picture of it (at least in mind). That means you must "think in hardware". A counter is not a heap of characters like c=c+1, instead its a chain of registers with logic to calculate the next counter value. Having that in mind you can write down c=c+1 easily. > Can someone tell me how to go about decoding this project. You have some hints for sure: - the surrounding and connected circuit and its function - a register description and a functional description of the design itself I would dig the design top-down: from the pins connected to the "real world" down to the registers of counters...
You may get an overview by creating the RTL (Register-Transfer-Logic) diagram. (I am unfortunately not able to tell you the exact steps to get it, but you may read it in the help). This view is usually hierarchically organized, so that you may advance from coarse to fine details. This view will you tell much about signal- (data-)flow throughout the whole project. It is, however, a non-trivial task for an unexperienced, to get the clue. But there is no way around. Bite through. :-) As these "opportunities" mostly occur when there is something wrong, and the boss tells you, to "just have a look - it must be something simple", you are about to dive into a venture. Good luck. One major issue for somebody coming from procedural programming is the intuitive but wrong assumption that the VHDL-Code is a procedural description as well - despite "knowing" (from numerous warnings about it) - that VHDL is (mostly) a structural description. Whenever you are worried about a obviously contradictory, strange assignment or sequence, reconsider this fact. As an anchor I would recommend you to read a part of a tutorial considering concurrent expressions/statements. It is, even with these countermeasures, a hard thing to overcome habit.
Klaus wrote: > that the VHDL-Code is a procedural description as well - despite > "knowing" (from numerous warnings about it) - that VHDL is (mostly) a > structural description. By the way: thats valid for Verilog as well... ;-) Even if the syntax is looking a little bit "C-ish" it ist DEFINITIVELY NOT a programming language! Otherwise it would be known as a HPL instead as a HDL...
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