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Forum: FPGA, VHDL & Verilog No feasible entries for infix operator "="


Author: VHDL New user (darylczj1995)
Posted on:

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Hi all! i am new to VHDL and i was ask to write a program in VHDL to 
implement a 3-input sequential Poller. The Poller has three inputs 
representing three devices. A device request service by asserting its 
input. On every clock cycle, the polling machine checks the status of 
the three input devices and generates an output code that identifies the 
asserted input(device) to be serviced, the device with the highest 
priority is selected. Each input is assigned a fixed priority denoted by 
its subscript; 3 is the highest priority and 1 is the lowest priority. 
To prevent "starving" the lower devices, the same asserted input is 
never selected on two successive pollings unless there are no other 
asserted pins.
Poller.png

------------------------------------------------------------------------ 
--------
    library ieee;
    use ieee.std_logic_1164.all;
    
    entity poller is port
    ( 
      req        : in std_logic_vector(3 downto 1):="000";
      clk,nreset : in std_logic_vector;
      ack        : out std_logic_vector(1 downto 0)
      );
    
    end poller;
    
    architecture behave of poller is
      
    type states is (none,req1,req2,req3);
      signal state : states;
    
    begin
     
     moore : process(clk, nreset)
     begin
       
      if(nreset = '1') then
       state <=none;
       
      elsif(clk' event and clk = '1')then
     
     case state is
     when none =>
                  if req(3)= '1' then
                    state <= req3;
                  elsif req(2)='1' then
                    state <= req2;
                  elsif req(1)='1' then
                    state <= req1;
                  end if;
                  
      when req1 =>
                  if req(3)= '1' then
                    state <= req3;
                  elsif req(2)='1' then
                    state <= req2;
                  elsif req(1)='1' then
                    state <= req1;
                  else
                    state <= none;
                  end if;
        
      when req2 =>
                  if req(3)='1' and req(2)='0' and req(1)='0' then
                    state <= req3;
                  elsif req(3)='1' and req(2)='1' and req(1)='0' then
                    state <= req3;
                  elsif req(3)='1' and req(2)='0' and req(1)='1' then
                    state <= req3;
                  elsif req(3)='0' and req(2)='1' and req(1)='0' then 
                    state <= req2;
                  elsif req(3)='0' and req(2)='0' and req(1)='1' then
                    state <= req1;
                  else
                    state <= none;
                  end if;
        
      when req3 =>
                  if req(3)='1' and req(2)='0' and req(1)='0' then
                    state <= req3;
                  elsif req(3)='1' and req(2)='1' and req(1)='0' then
                    state <= req2;
                  elsif req(3)='1' and req(2)='0' and req(1)='1' then
                    state <= req1;
                  elsif req(3)='0' and req(2)='1' and req(1)='0' then 
                    state <= req2;
                  elsif req(3)='0' and req(2)='1' and req(1)='1' then 
                    state <= req2;
                  elsif req(3)='0' and req(2)='0' and req(1)='1' then
                    state <= req1;
                  else
                    state <= none;
                  end if;
                  
                end case;
              end if;
            end process;
            
      ack <= "00" when (state= none) 
    else "01" when (state= req1)
    else "10" when (state= req2)
    else "11";
      
    end behave;
        

While compiling the code in Modelsim PE Student I get the following 
error

    ** Error: C:/Users/work/h/vhdl/poller.vhd(24): No feasible entries 
for infix operator "=".
    ** Error: C:/Users/work/h/vhdl/poller.vhd(24): **Type error 
resolving infix expression "=" as type std.STANDARD.BOOLEAN.**
    ** Error: C:/Users/work/h/vhdl/poller.vhd(27): No feasible entries 
for infix operator "=".
    ** Error: C:/Users/work/h/vhdl/poller.vhd(27): Bad expression in 
right operand of infix expression "and".
    ** Error: C:/Users/work/h/vhdl/poller.vhd(27): Type error resolving 
infix expression "and" as type std.STANDARD.BOOLEAN.
    ** Error: C:/Users/work/h/vhdl/poller.vhd(91): VHDL Compiler exiting


Any help is appreicated:)

: Edited by Moderator
Author: VHDL New user (darylczj1995)
Posted on:

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i found a solution to it
instead of
library ieee;
use ieee.std_logic_1164.all;

entity poller is port
( 
  req        : in std_logic_vector(3 downto 1):="000";
  clk,nreset : in std_logic_vector;
  ack        : out std_logic_vector(1 downto 0)
  );

end poller;

it is
library ieee;
use ieee.std_logic_1164.all;

entity poller is port
( 
  req        : in std_logic_vector(3 downto 1):="000";
  clk,nreset : in std_logic;
  ack        : out std_logic_vector(1 downto 0)
  );

end poller;

i made a mistake at my entity.

: Edited by Moderator

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