Forum: FPGA, VHDL & Verilog How to set the startup clock in PlanAhead?

Author: xilinx_newbee (Guest)
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I'm making my first steps in PlanAhead v14.7. When configuring my Nexys 
2 board with the bitstream generated from my PA project in IMPACT, I 
receive a warning about CCLK being used as the startup clock and that 
JtagClock is needed, because the device is going to be configured with 
JTAG. IMPACT patches the bitstream file in memory eventually to fix it 
and loads it into the device.

This does not work in Adept however, which complains that it will not 
work with CCLK.

I know how to set the startup clock ISE, but I have now idea how to 
specify the startup clock in PlanAhead. Anybody?

Author: xilinx_newbee (Guest)
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This seems to work: Go to "Program and Debug|Bitstream Settings" in the 
"Flow Navigator" and enter

-g StartUpClk:JtagClk

into the "More Options" field. However, doing this neither enables the 
"Apply" button, nor makes "OK" store anything. I have to toggle one of 
the other options back and forth to make PA register the changes the 
"More Options" field.


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