EmbDev.net

Forum: FPGA, VHDL & Verilog [HELP] VHDL "cant infer register."


Author: Paulo Henrique Silva (Guest)
Posted on:

Rate this post
0 useful
not useful
The Quartus is detecting an error in my code, the error is this:

Error (10821): HDL error at state_machine.vhd(27): can't infer register 
for "atual" because its behavior does not match any supported register 
model

I do not know how to solve. I need to use "case" and "type" because my 
teacher asked.

I ask for help to solve. The code is below.
Thank you.
--DECLARAÇÃO DE BIBLIOTECAS

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
--LIBRARY WORK;
--USE work.digital_filter_package.all;

--DECLARAÇÃO DA ENTIDADE

ENTITY state_machine IS
  PORT(
    clk,d: IN STD_LOGIC
  );
END ENTITY state_machine;

--DECLARAÇÃO DA ARQUITETURA DA ENTIDADE

ARCHITECTURE behavioral OF state_machine IS
  TYPE estado IS(amostrar,naoamostrar);
  SIGNAL cancannot: STD_LOGIC;
  SIGNAL atual: estado := naoamostrar;
BEGIN
  contandoeamostrando: PROCESS(clk,d,atual)
    VARIABLE count: INTEGER := 0;
  BEGIN
    CASE atual IS
      WHEN amostrar =>
        cancannot <= '1';
        IF(RISING_EDGE(clk)) THEN
          count := 0;
          atual <= naoamostrar;
        END IF;
      WHEN naoamostrar =>
        cancannot <= '0';
        IF(RISING_EDGE(clk)) THEN
          IF(count<3333333) THEN
            count := count + 1;
          ELSE
            atual <= amostrar;
          END IF;
        END IF;
    END CASE;
  END PROCESS;
END ARCHITECTURE;

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Paulo Henrique Silva wrote:
> can't infer register for "atual" because its behavior does not match any
> supported register model
The synthesizer cannot transfer your VHDL description to a hardware 
inside the FPGA.

And thats the problem:
IF(RISING_EDGE(clk)) THEN
Indeed not that line is the problem, but the place where it is located 
inside the code and also that this line is doubled inside the 
description. Where did you see this coding style? Nowhere? Its your 
idea?

If you want describe hardware in a synthesizeable manner you must do it 
in a way the synthesizer understands. And what the synthesizer 
understands is written in the synthesizers user guide. So have a close 
look for XST UG.

Try it a little more the "usual way". This here will be synthesizeable 
for sure, because its a straightforward synchronous design:
  contandoeamostrando: PROCESS(clk)
    VARIABLE count: INTEGER := 0;
  BEGIN
    IF(RISING_EDGE(clk)) THEN   -- a totally synchronous design

      CASE atual IS
        WHEN amostrar =>
          cancannot <= '1';
          count := 0;
          atual <= naoamostrar;
        WHEN naoamostrar =>
          cancannot <= '0';
          IF(count<3333333) THEN
            count := count + 1;
          ELSE
            atual <= amostrar;
          END IF;
       END CASE;

     END IF; 
  END PROCESS;

: Edited by Moderator

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.