Paulo Henrique Silva wrote:
> can't infer register for "atual" because its behavior does not match any
> supported register model
The synthesizer cannot transfer your VHDL description to a hardware
inside the FPGA.
And thats the problem:
IF(RISING_EDGE(clk)) THEN
Indeed not that line is the problem, but the place where it is located
inside the code and also that this line is doubled inside the
description. Where did you see this coding style? Nowhere? Its your
idea?
If you want describe hardware in a synthesizeable manner you must do it
in a way the synthesizer understands. And what the synthesizer
understands is written in the synthesizers user guide. So have a close
look for XST UG.
Try it a little more the "usual way". This here will be synthesizeable
for sure, because its a straightforward synchronous design:
1 | contandoeamostrando: PROCESS(clk)
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2 | VARIABLE count: INTEGER := 0;
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3 | BEGIN
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4 | IF(RISING_EDGE(clk)) THEN -- a totally synchronous design
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5 |
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6 | CASE atual IS
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7 | WHEN amostrar =>
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8 | cancannot <= '1';
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9 | count := 0;
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10 | atual <= naoamostrar;
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11 | WHEN naoamostrar =>
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12 | cancannot <= '0';
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13 | IF(count<3333333) THEN
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14 | count := count + 1;
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15 | ELSE
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16 | atual <= amostrar;
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17 | END IF;
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18 | END CASE;
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19 |
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20 | END IF;
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21 | END PROCESS;
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