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Error Loading Design
von VHDL N. (darylczj1995)

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Hi

I need to design an 4-bit comparator using hierarchical design. I have 
the following code, which I think is right, but when i try to simulate 
it in modelsim launch me an error saying error loading design.

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---Design code---

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.std_logic_arith.all;

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use ieee.std_logic_unsigned.all;

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entity bitcompare4 is port

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    ( 

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      A,B : in bit_vector(3 downto 0);

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      AgtB_o,AeqB_o,AltB_o : out bit

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      );

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end bitcompare4;

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architecture behave of bitcompare4 is 

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component bitcompare port

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  (

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    A,B,AgtB_i,AeqB_i : in bit;

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    AgtB_o,AeqB_o : out bit

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  );

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end component; 

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signal AgtB_o1,AeqB_o1 : bit_vector(3 downto 0);

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signal gnd, vcc : bit;

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begin

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gnd <= '0';

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vcc <= '1';  

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U1 : bitcompare port map 

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  (

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    A      => A(3),

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    B      => B(3),

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    AgtB_i => gnd,

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    AeqB_i => vcc,

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    AgtB_o => AgtB_o1(3),

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    AeqB_o => AeqB_o1(3)

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  );

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U2 : bitcompare port map 

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  (

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    A      => A(2),

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    B      => B(2),

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    AgtB_i => AgtB_o1(3),

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    AeqB_i => AeqB_o1(3),

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    AgtB_o => AgtB_o1(2),

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    AeqB_o => AeqB_o1(2)

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  );

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U3 : bitcompare port map 

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  (

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    A      => A(1),

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    B      => B(1),

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    AgtB_i => AgtB_o1(2),

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    AeqB_i => AeqB_o1(2),

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    AgtB_o => AgtB_o1(1),

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    AeqB_o => AeqB_o1(1)

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  );

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U4 : bitcompare port map 

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  (

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    A      => A(0),

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    B      => B(0),

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    AgtB_i => AgtB_o1(1),

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    AeqB_i => AeqB_o1(1),

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    AgtB_o => AgtB_o1(0),

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    AeqB_o => AeqB_o1(0)

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  );

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  AgtB_o <= AgtB_o1(0);

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  AeqB_o <= AeqB_o1(0);

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  AltB_o <= not ( AgtB_o1(0) or AeqB_o1(0));

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end behave;

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---------------------------------------------------------------------------

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---TestBench---

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library ieee;

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use ieee.std_logic_1164.all;

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entity bitcompare4_tb is

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end bitcompare4_tb;

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architecture bitcompare4 of bitcompare4_tb is

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  component bitcompare4 port

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  (

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    A,B : in std_logic_vector(3 downto 0);

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    AgtB,AeqB,AltB : out std_logic

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  );

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end component;

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signal A1,B1 : std_logic_vector(3 downto 0);

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signal AgtB1,AeqB1,AltB1 : std_logic;

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begin

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  U1 : bitcompare4 port map 

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    ( 

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      A      => A1,

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      B      => B1,

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      AgtB   => AgtB1,

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      AeqB   => AeqB1,

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      AltB   => AltB1

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    );

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A1 <= "0000", "0010" after 20 ns, "1010" after 40 ns, "1011" after 60 ns;

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B1 <= "0000", "0001" after 20 ns, "1010" after 40 ns, "1100" after 60 ns;

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end bitcompare4;


  


  



  

  
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    Re: Error Loading Design
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

      

      

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Did you see that a few lines above the edit box?
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   [vhdl]VHDL code[/vhdl]


VHDL N. wrote:
> when i try to simulate it in modelsim launch me an error saying error
> loading design.
How do you try to simulate it?
Did you start a new project and add those two code/files?
What (or where) is bitcompare?

I don't think its a good idea to use the name "bitcompare4" several 
times (although it does not generate the problem here).
But for sure it isn't a good idea to use "bit" and "std_logic" as the 
same (see the port in your entities port and the port of the component).
And also the port names MUST be the same in the entity port definition 
and the components port.

After addig the missing bitcompare and having corrected the mistakes I 
get some (little bit dubious) result with ISIM...

  


  



  

  
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    Re: Error Loading Design
  


  

    

      von
      
        VHDL N.
        (darylczj1995)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Thanks Lothar Miller, i found a solution to it already.

  


  




  

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