david wrote:
> I tried to declare a in  the proccess and to move the outb<=a; to the
> process as well-still doesnt work-> in the simulation outb is
> undefined...
So the problem is NOT in the posted code...

1. Usually a VHDL description begins with "library ieee;". Thats missing 
here.
2. What toolchain do you use?
3. What is your testbench?
4. What do you expect and what do you get instead?

> in the simulation outb is undefined...
What does clk look like? Is it toggling?

For me its simulating (some kind of) "well" in the behavioural 
simualtion...

But you have a VERY big mistake in your code!
> process(clk)
>   begin
>     a<=not(a);
>   end process;
The sensitivity list is WRONG, because the process is NOT dependent on 
the clk. Its only dependent on any change of a.
You must get one thing very clear: the sensitivity list is ONLY for the 
simulator. It ist not used by the synthesizer, its simply ignored by 
the synthesizer!

And therefore the process MUST be this way:
> process(a)
>   begin
>     a<=not(a);
>   end process;
And then you can see: theres absolutely no clk involved in the 
description!


OK, lets go one step backwards...
david wrote:
> I try to right a code that in every, say, clock change(not only a rise)
> it will change the out bit from 1 to 0 or from 0 to 1.
Because VHDL is a hardware description language you must have a 
"picture" or a sketch or something in front of you (or in your mind) you 
can describe.
What piece of hardware can react on either clock edge? Is there a kind 
of "double clock flipflop" inside your FPGA/CPLD?
No? Then you cannot use a description of such a piece of hardware in 
your code.

So again one step back: what do you want to do?

david wrote:
> the simulation you uploaded was recieved from running my code with no
> changes?
Yes, indeed. The "test bench" is attached here. I used Xilinx ISE ISIM 
for simulation.

Keep in mind: I ran a pre synthesis behavioural simulation. Maybe a 
post synthesis timing simulation will get your result...