Although I am familiar with hardware in general, I am fairly new to ASIC design. When you design a register based IP core in general, usually the IP core is controlled by writing to registers. How would you design a core that is controlled by the registers? I am familiar with how data path and registers work, but I am not quite sure how to design a IP core with how the registers are used to controlled the data path or any IP core logic. Do happen to have a link to any documentation? Thanks.
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
Log in with Google account
No account? Register here.