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Forum: FPGA, VHDL & Verilog Carry Look Ahead Adder showing U at last bit position in SUM


Author: Rohan Narkhede (Guest)
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Hi,

I am getting U at the last bit position of SUM when I add two 32 bit 
numbers a and b by carry look ahead adder in VHDL.

my code is as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity cla_nbits is
generic (N : integer := 32);
    Port ( a : in STD_LOGIC_VECTOR (N-1 downto 0);
           b : in STD_LOGIC_VECTOR (N-1 downto 0);
           cin : in STD_LOGIC;
           sum : out STD_LOGIC_VECTOR (N-1 downto 0);
           cout : out STD_LOGIC);
end cla_nbits;

architecture Behavioral of cla_nbits is

signal g : STD_LOGIC_VECTOR (N-1 downto 0);
signal p : STD_LOGIC_VECTOR (N-1 downto 0);
signal c : STD_LOGIC_VECTOR (N-1 downto 0);

begin

g <= a and b;
p <= a xor b;
c(0) <= cin;

p1: process(p,g,c,cin)
begin

c(1) <= g(0) or (p(0) and cin);
for i in 1 to N-2 loop
    c(i+1) <= g(i) or (p(i) and c(i));
    end loop;
    
cout <= g(N-1) or (p(N-1) and c(N-1));

end process;

sum <= p xor c;
--sum(N-1 downto 0) <= p(N-1 downto 0) xor c(N-1 downto 0);

end Behavioral;

and the corresponding test bench i prepared is as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_cla_nbit is
--  Port ( );
end tb_cla_nbit;

architecture tb of tb_cla_nbit is

component cla_nbits 
generic (N : integer := 32);
    Port ( a : in STD_LOGIC_VECTOR (N-1 downto 0);
           b : in STD_LOGIC_VECTOR (N-1 downto 0);
           cin : in STD_LOGIC;
           sum : out STD_LOGIC_VECTOR (N-1 downto 0);
           cout : out STD_LOGIC);
end component;


signal at, bt : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal cint : STD_LOGIC := '0';
signal sumt : STD_LOGIC_VECTOR (31 downto 0);
signal coutt : STD_LOGIC;

begin

uut1: cla_nbits port map (a=>at, b=>bt, cin=>cint, sum=>sumt, cout=>coutt);

p1: process
begin
at <= X"FFFFFFFF";
bt <= X"00000001";
wait for 50 ns;

at <= X"FFFFFFFF";
bt <= X"00000000";
cint <= '1';
wait for 50 ns;

at <= X"1A7E34B5";
bt <= X"11111111";
cint <= '1';
wait for 50 ns;

end process;
end tb;

Please let me know how to see the LSB bit in the SUM.

: Edited by Moderator
Author: Duke Scarring (Guest)
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You need to drive the signal from one process only:
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity cla_nbits is
    generic (N : integer := 32);
    port (a    : in  std_logic_vector (N-1 downto 0);
          b    : in  std_logic_vector (N-1 downto 0);
          cin  : in  std_logic;
          sum  : out std_logic_vector (N-1 downto 0);
          cout : out std_logic);
end cla_nbits;

architecture Behavioral of cla_nbits is

    signal g : std_logic_vector (N-1 downto 0);
    signal p : std_logic_vector (N-1 downto 0);
    signal c : std_logic_vector (N-1 downto 0);

begin

    g    <= a and b;
    p    <= a xor b;

    p1 : process(p, g, c, cin)
    begin
        c(0) <= cin;  -- not usable for the same signal outside the process

        c(1) <= g(0) or (p(0) and cin);
        for i in 1 to N-2 loop
            c(i+1) <= g(i) or (p(i) and c(i));
        end loop;

        cout <= g(N-1) or (p(N-1) and c(N-1));

    end process;

    sum <= p xor c;
--sum(N-1 downto 0) <= p(N-1 downto 0) xor c(N-1 downto 0);

end Behavioral;

Author: Lothar Miller (lkmiller) (Moderator)
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Rohan Narkhede wrote:
> my code is as follows:
> _____________________________________________________________________
Pls do not use that stylish line, but instead the [ vhdl ] tags as shown 
a few lines above each edit box:
Reply
Rules — please read before posting
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Author: Rohan Narkhede (Company: student) (rohan_n)
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Thank you so much Duke Scarring. This really works!

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