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Forum: FPGA, VHDL & Verilog multiple schematicsheet connections


Author: Hugh Smith (Company: Hugh T Smith) (smithh)
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I'm currently building a project with multiple schematics because I work 
better with hardware than HDL. The problem I'm having is getting BUSS 
definitions to pass from 1 schematic to the other.

Screen_1 shows the source connections and Screen_2 shows the 
destination.
Screen_3 shows the error message when I synthesize.

I need a hardware expert to tell me whats going on, or is hardware an 
outdated concept.

Thanks in advance
Hugh

Author: Lothar Miller (lkmiller) (Moderator)
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Hugh S. wrote:
> I'm currently building a project with multiple schematics
With what toolchain?

> because I work better with hardware than HDL.
Thats an odd argument. Have a look at this (try google translate, its 
german): Beitrag "kruder Fehler bei FPGA-Programmierung (ISE WEBpack-Schematic)"
Those guys tried schematics, but ended a few days later with VHDL...

> or is hardware an outdated concept.
Its a dead end road.

Can you open or edit or simply view a 15 years old schematic with a new 
software version?
No?
Can you open a 15 year old text file?
Yes!

How do you compare two schematics?
How do you compare two text files?

Verilog and VHDL are simple text files...

: Edited by Moderator

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