Hi everyone,
I was under the impression that the bitorder of values in SystemVerilog
was lefttoright: MSbittoLSbit.
Recently, I wrote up a 11bitwide multiplexer:
module test_mux( input logic [10:0] input_a,
input logic override,
output logic [10:0] output_c);
parameter [10:0] constant = 11'h00F;
assign output_c = (override) ?
constant :
input_a;
endmodule

expecting the moresignificant bits to be zeros and the last four
lesssignificant bits to be ones. When I synthesized it and visualized
the result, though, I got the unexpected constant 11'h780 as my constant
input.
I tried an alternative:
parameter [10:0] constant = 11'h00F;
always_comb
begin
integer i;
for (i = 0; i < 11; i = i + 1)
begin
output_c[i] = (override) ?
constant[i] :
input_a[i];
end
end

and got the expected constant input to be 11'hf.
(a) Are the two above code snippets not the same??
(b) What is the expected bitorder in Quartus?
I'm ruling out that the RTL viewer is just rendering the values
incorrectly. To do so, for the unexpected result, I expanded the mux
input and saw that mux[0]: 1, mux[1]: 1 ... mux[10]:0, which would rule
out that Quartus' RTL viewer is just rendering the result incorrectly.
Thanks for taking a look, and I'd appreciate any leads on this!
Cheers!