Forum: FPGA, VHDL & Verilog SPI_slave testbench

Author: puka1012 (Guest)
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can someone please help me how to write the test bench for the spi_slave
from opencores.org.However there is a code for the test
bench(spi_loopback_test) along with the main design module but its for
both master slave parallel interface and in no ways it is related to
spi_slave for example(CPOL AND CPHA are different,PREFTECH number is
different).I tried my best to write the test bench code but its getting
complicated beacuse of its lengthiness.60 to 70 percent of the code i
assume i have done it and u can see in the attachment and if someone
could help me to finish it or provide the rest of the code in case you
have free time.spi_slave and spi_loopback_test are also attached.With
Reference to spi_loopback_tet i hav written the testbench code

: Moved by Moderator
Author: P. K. (pek)
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The simulation that comes along with the SPI IP seems to be for both, 
master and slave, so set it up with both (if you are not interested in 
the master, well then it serves just as simulation model...).

Author: Lothar Miller (lkmiller) (Moderator)
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puka1012 wrote:
> can someone please help me
Pls NO double posts, and NO English posts in the German forum.

I think I mentioned the second already several times, didn't I?


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