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Forum: FPGA, VHDL & Verilog Case statement choices cover only 4 out of 81 cases.


Author: puka1012 (Guest)
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how to get rid of this error?

I have added while others =>.Despite adding this,i am getting error

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Author: Lothar Miller (lkmiller) (Moderator)
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puka1012 schrieb:
> how to get rid of this error?
HOW and with WHICH code do you get this error?

READ your own question as if you know NOTHING about your specific 
problem. Does it make any sense? Rarely!

> I have added while others =>.Despite adding this,i am getting error
I assume that you have a VHDL code that uses a 2 bit std_logic_vector 
in a case statement. And because std_logic has 9 values it can have 
"U,X,H,L...1,0". Therefore with 2 bits you have 9*9 = 81 possibilites: 
"UU", "UX", "XU" ... "00". In your case you use only "00", "01", "10" 
and "11". That means 77 possibilites are not covered in your case 
statement. The "when others" includes those 77 cases.

Thats how its done all around the world:
To get rid of this error you could decode "00", "01", "10" explicitly, 
and redirect all others (including the "11") to the "when others" case.



And once more:
please post your ENGLISH questions in the ENGLISH spoken embdev.net!
mikrocontroller.net is the GERMAN part of the forum!

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