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Forum: FPGA, VHDL & Verilog SPI slave open core simulation diagram


Author: puka1012 (Guest)
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Hi all,

If someone has tried the spi slave implementation from open 
cores.org,can you please post siumlation diagram with little 
explanation.However,this code doesnt seem to be a simple spi slave 
implementation as it has too many inputs and output ports and most of 
the signals are unknown.I am uploading the code for the quick 
reference.If someone has time,please run it in the modelsim and let me 
know

: Moved by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
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puka1012 wrote:
> the spi slave implementation from open cores.org
I had finished reading the code after those 2 lines:
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
Its obviously a beginners code. That can be easily seen throughout the 
code at such things:
- a "double-clocked" process
- the sensitivity list has too much signals in it
    in_transfer_proc: process (clk_i, wren_i, wr_ack_reg) is -- clk_i is enough here!
    begin
        if clk_i'event and clk_i = '1' then     -- a clock!
             ...
        end  if;

        if clk_i'event and clk_i = '1' then     -- and once more a clock? :-o
             ...
        end  if;
    end process in_transfer_proc;

And this: a clocked process which has also a async part. Wow!
    out_transfer_proc : process ( clk_i, do_transfer_reg, di_req_reg,
                                  do_valid_A, do_valid_B, do_valid_D, 
                                  di_req_o_A, di_req_o_B, di_req_o_D) is
    begin
        -- CLOCKED !!!
        if clk_i'event and clk_i = '1' then 
          ....
        end if;
        
        -- COMBINATORIAL !!!
        do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
        di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
    end process out_transfer_proc;


Its easy to implement a thoroughly synchronous(!!) SPI slave interface 
in less then 100 lines of code. See the 
Beitrag "Re: Erfahrung mit SPI Slave und Spartan 6 FPGA?" (try google 
translator)...

: Edited by Moderator
Author: Susa Kl (suhas_s)
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Can you please tell me what is PREFETCH and prefetch look cycle and its 
implementation in the code??...I know there are simple ways to implement 
it but i really want to understand this

: Edited by User
Author: Lothar Miller (lkmiller) (Moderator)
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Suhas S. wrote:
> Can you please tell me what is PREFETCH and prefetch look cycle and its
> implementation in the code??
Have a look at the code: that "PREFETCH" its a wrong name for "i have 
nearly transmitted all of the bytes". That is signalled to the "outer 
world" with the di_req_o port. That signal is generated form the 
di_req_next with a very obscure sync stage and a 5 bit shift-register 
in between...

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