EmbDev.net

Forum: FPGA, VHDL & Verilog I am having difficulties with synthesis


Author: Manish Singh (Guest)
Posted on:

Rate this post
0 useful
not useful
dear all, I am in progress in finishing a design and nead to get it 
ready for Synthesis. In  the Simulation it workrs fine and does what 
required.

The problem with synthesis is timing cannot be met. I have also spended 
a lot of Flipflops allready and it still does not work.

which possibilitys do exist to solve this problem general?

Author: P. K. (pek)
Posted on:

Rate this post
0 useful
not useful
Manish Singh wrote:
> which possibilitys do exist to solve this problem general?

- Review where the worst paths are (STA results) and why they
  are so long. Think over what went bad and what you can do
  to reduce the length of those paths.
- Reduce the number of logic Levels between registers (large
  "if-elsif-elsif-elsif-..." constructs are particularly bad)
- If the timing is missed just a very small bit, try with other
  fitter settings/seed
- Reduce your system clocking frequency
- Take a faster FPGA

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Manish Singh wrote:
> which possibilitys do exist to solve this problem general?
Use STA (static timing analysys) to find the critical path. Check out 
what components are involved and try to improve that path.

Another possibility would be to say WHAT FPGA you usr and WHAT frequency 
you want. Maybe its simply not possible...

Author: Manish Singh (Guest)
Posted on:

Rate this post
0 useful
not useful
dear all, thanks for this informations

I allready inspected all the crititcal patha, but most things are 
generated by coregen Generator automatically and can hardly be traced

moreover the Signal names are weird

taking a fast fpga is not easy, will customer will have to decide this

and the fpga frequency is also fixed


i will continue on monday with this issues.

thanks very much

Author: Alexander F. (alexf91)
Posted on:

Rate this post
0 useful
not useful
In case  you are using multiple clock domains: Some tools assume all 
paths between clock domains valid, unless you declare them as false 
paths. This leads to some very tight timing requirements by default.

Author: Manish Singh (Guest)
Posted on:

Rate this post
0 useful
not useful
This issue is already under Investigation. It seems to be correctly done 
according to an FPGA expert's opinion. There are only 2 Domains with a 
high Speed Input data source.

The whole thing seems more related the output of the coregen's cores. 
they seem not to be qualified for the required speeds.

Author: Alexander F. (alexf91)
Posted on:

Rate this post
0 useful
not useful
Just out of interest, what core, FPGA, software and frequency is 
involved?

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.