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Forum: FPGA, VHDL & Verilog Synthesizer Problems


Author: Hugh Smith (Company: Hugh T Smith) (smithh)
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Lines 46 and 47, when synthesized, generate a 6 digit shift register as 
verified by an RTL schematic, as expected.

Lines 48 and 50 only generate a 3 digit register, regardless of the 
assignment type.

Any of the choices synthesize without errors but only 46,47 simulate 
correctly.

Question 1 is why.
Question 2.  How do I know, in a more complex design, that this type of 
error won't occur again without doing a us by us analysis.


Hugh

Author: Lattice User (Guest)
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Hugh S. wrote:

>
> Question 1 is why.

Line 50 should be
    ShiftReg[5:0] <= { ShiftReg[4:0], btn };

> Question 2.  How do I know, in a more complex design, that this type of
> error won't occur again without doing a us by us analysis.
>

Always look at the warnings, in this case there is certainly one telling 
you about pruning ShiftReg[0]

Next time please don't post source code as pictures.

Author: Hugh Smith (Company: Hugh T Smith) (smithh)
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Lattice User,

Thank you for your response.  It was right on.  I don't know how long I 
stared at that code and didn't see the error.

Hugh

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