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Forum: FPGA, VHDL & Verilog SPI read and write registers (32 bit data)


Author: puka1012 (Guest)
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Hi,

My microcontroller acts as a master and FPGA(Altera) as a slave.I have 
to send the address from microcontroller and FPGA should answer.My FPGA 
answers "FPGA not working" if it reads any other address other than 
AA000000.The main motto is to mkae it read AA000000.However i worked 
with 8 bit and it worked fine but i have no idea how to do it for 32 bit 
data.with the following code my FPGA reads 2A000000 but with display 
"FPGA not working " since it can answers only for AA000000.Anyone who 
can help me with the changes in the code


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity spiregister is
  generic (
    VersionMajor : integer;
    VersionMinor : integer
  );
  port(
    cs0       : in  std_logic;
    cs1       : in  std_logic;
    clk       : in  std_logic;
    mosi      : in  std_logic;
    miso      : out std_logic
  );
end spiregister;



architecture arc of spiregister is
  type register_t is array (0 to 19) of std_logic_vector(31 downto 0);
  signal wr          : std_logic;
  signal addr        : std_logic_vector(6 downto 0);
  signal reg_value   : std_logic_vector(31 downto 0);
  signal registers   : register_t;
  signal bit_out     : std_logic_vector(31 downto 0);
  signal bit_in     : std_logic_vector(31 downto 0);

begin
process(clk, cs0)
  variable count       : unsigned(6 downto 0);
begin
  if cs0 = '1' then
    wr   <= '0' ;
    bit_out <= "00000000000000000000000000000000";
    bit_in  <= "00000000000000000000000000000000";
    count := "0000000";
  elsif clk = '1' and clk'event then
    if ( count = x"00" ) then
      wr <= mosi;
    elsif ( count < x"08" ) then
      addr <= addr(5 downto 0) & mosi;
    elsif ( count = x"08" ) then
      if( addr = "0000000") then
        bit_out <= x"000000AA";
      elsif ( addr = "0000001") then
        bit_out <= std_logic_vector(to_unsigned(VersionMajor,32));
      elsif ( addr = "0000010") then
        bit_out <= std_logic_vector(to_unsigned(VersionMinor,32));
      else
        bit_out <= registers(to_integer(unsigned(addr)));
      end if;
      bit_in <= bit_in(30 downto 0) & mosi;
    elsif ( count < x"10" ) then
      bit_in <= bit_in(30 downto 0) & mosi;
    elsif ( count = x"10" ) then
      if ( wr = '1') then
        if ( addr /= "0000000" and addr/= "0000001") then
          registers(to_integer(unsigned(addr))) <= bit_in;
        end if;
      end if;
      bit_out <= bit_out(30 downto 0) & '0';
    elsif ( count < x"18" ) then
     bit_out <= bit_out(30 downto 0) & '0';
    elsif(count = x"18") then
    elsif(count < x"20") then
     bit_out<= bit_out(30 downto 0) & '0';
    elsif(count = x"20") then
    elsif(count < x"28") then
     bit_out<= bit_out(30 downto 0) & '0';
    elsif(count = x"28") then



end if;

    count := count + 1;

  end if;
end process;

miso <= bit_out(31);



end arc;

Author: Lothar Miller (lkmiller) (Moderator)
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puka1012 wrote:
> My FPGA answers "FPGA not working"
What do you see in simulation? A SPI interface can be put fairly easy on 
a testbench...

: Edited by Moderator
Author: Susa Kl (suhas_s)
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Hi,


MISO is completely nil.I have attached the simulation diagaram


bit_out<= bit_out(30 downto 0) & '0';
bit_out <= registers(to_integer(unsigned(addr)));
if ( addr /= "0000000" and addr/= "0000001") then
          registers(to_integer(unsigned(addr))) <= bit_in;
        end if;

Can you also tell me what does the above lines actually does..I am 
confused

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