Forum: FPGA, VHDL & Verilog Netlist theoretical doubt

Author: Junior Hpc (Company: University) (junior_hpc)
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Hello. While I was studying the theory I have got that if you write a 
netlist, then you can generate a bitfile, load it into the FPGA and 
execute the program. I have done a double check with my Xilinx FPGA:
-I created a VHDL program with Vivado
-I defined the constraints (link inputs and outputs of my VHDL program 
to the actual pins of my FPGA) on a new file (.xdc)
-I generated the bitfile, loaded it into the FPGA and tested the program 
(it worked)
-Finally I exported the netlist (still with Vivado) generating the .edn 

Next, to check if the theory was correct I have done:
-I created a new post-synthesis project
-I imported the netlist previously generated (without the constraint 
-I tried to generate the the bitfile but I got errors. I solved by 
creating the constraints (.xdc).

So, my question is: is there the possibility to define the constraints 
into the netlist or every time I import a netlist should I have to 
create an external file in order to define the constraints?


Author: Klakx (Guest)
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netlist is just a schematic without layout Information. Without 
constraints the place&route tool could place two elements with a 
Connection over the whole chip. for slow frequencies it works but for 
fast signals this Connection would have a too high capacitive load. So 
you need frequency information, among other things, in your constraint 

it is possible in xilinx to give some constraints by attributes but imho 
the best way is to add a constraint file and avoid attributes


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