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Forum: FPGA, VHDL & Verilog From netlist to VHDL


From netlist to VHDL
von Junior H. (Company: University) (junior_hpc)

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Hello. Normally, a user, writes the VHDL code and then he runs the 
synthesis in order to generate the netlist. I'm facing the opposite 
problem: with JHDL I have generated the netlist and once I import it in 
a new empty project on Vivado (I have Xilinx FPGA) I can not run the 
synthesis because Vivado tells me that I don't have any VHDL file in my 
project. Is possible starting from a netlist, create a HDL file? Well, I 
know that the netlist represents the interconnection of a specific HDL 
file (so I guess it is possible) but I don't understand how to link HDL 
and .edn files.

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Re: From netlist to VHDL
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Junior H. wrote:
> I can not run the synthesis
You don't need to run synthesis, because the output of the synthesizer 
is a netlist...

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Re: From netlist to VHDL
von Junior H. (Company: University) (junior_hpc)

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Lothar M. wrote:
> Junior H. wrote:
>> I can not run the synthesis
> You don't need to run synthesis, because the output of the synthesizer
> is a netlist...

In order to generate the bitfile using Vivado, I click on "Generate 
Bitstream" but it prints out this message:

There are no implementation results available. OK to launch synthesis 
and implementation? 'Generate Bitstream' will automatically start when 
synthesis and implementation completes.

It forces me to run the synthesis and then implementation. While it is 
running the synthesis it prints out the error:"Unable to run synthesis. 
No HDL sources found in project".

Do you know any other tool to generate the bitfile from the netlist for 
Xilinx FPGA? My FGPA is Xilinx AC701 and they only officially provide 
Vivado suite.

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Re: From netlist to VHDL
von Junior H. (Company: University) (junior_hpc)

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I have been solving creating a post-synthesis project but now I get 
these 2 design errors:
-[Place 30-494] The design is empty
-[Common 17-69] Command failed: Placer could not place all instances

Does anybody have idea why I get these errors? I just created a 
post-synthesis project importing the netlist. Vivado prints out that 
error while it is trying to generate the bitfile.

Thanks

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