lkb wrote:
> Yes, it works in testbench/sim, but not in hardware
I'm more the VHDL man, but as far as I see you have designed a latch,
which is not good design practice on an FPGA. Additionally this latch
has a combinational enable, which is far more worse and will lead to
unpredictable behaviour. Keep in mind although all off the registers of
mux_cmd_r change at the (nearly) same time, the wiring and the mux
decoder logic afterwards lead to spikes and spurious latching of
undesired values.
Additionally I assume that the mux_cmd_r is not synchronous to the
clock and you therefore will have a problem with an inconsitent value in
that register: what if the mux_cmd changes at the (almost) very same
time the clock rises? Then maybe due to setup/hold-timing violation some
of the bits take the new value, and some of them keep the old value. And
ouch, for one clock cycle you have a wrong mux_cmd_r value. Same
concerns the behaviour of the mux_sel_r value.
You must NOT think of the TEST_BUS_r as one singal. Inside the FPGA
there are 12 single bits with their very own wiring and LUTs and
behaviour...
BTW:
TEST_BUS_r is not the correct name, because its not a "r"egister. It
should be named TEST_BUS_l from "l"atch...