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Forum: FPGA, VHDL & Verilog SPI slave in FPGA


Author: SparkyT (Guest)
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Hi all,
a couple questions for the gurus in this forum,
I am writing an FSM based SPI slave for mode 0,0 in a FPGA.

First question is, do I need to double register the 3 incoming lines?
(serial_clk, MOSI and CSn)

So, far i am double registering with a 100 MHz fpga system clock, and 
the serial_clk is about 10 MHz.
For example, the CSn becomes, CSn_latched and CSn_last.
Everything inside the fpga happens under a rising_edge of the 100MHz 
clk, and I detect rising and falling edges of the serial clk with the 
help of the double registers (ser_clk_latched and ser_clk_last).
The FSM transition are happening with the fast clk.

Now, when I am ready to register the MISO line, I am still based on the 
double registers of the serial clk, and it feels that its very tight
for the master to sample the MISO line on the falling edge of the serial 
clk, while I update the line, 2 clock (100MHz) pulses later.

Second question, related to the first, is 100 MHz fast enough to double 
register the 10MHz?

Because of a different error, I cant run (so far) a post layout 
simulation to see timmings (will do though). pre-synth and post-synth 
simulation show correct behaviour, but finally trying on real hw, it 
fails.

Hope all this makes sense...

Author: P. K. (pek)
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The need for a double registering (synchronisation, meta-stability 
filter, etc.) is discussed controversially when design runs in an FPGA, 
so I will not elaborate on this.

Technically, you can consider the double registering of your inputs as a 
pipeline adding (2 fast clock cycles) latency to your inputs. As all 
inputs (clk, e, mosi) suffer the same amount of latency this is not a 
problem so far. You detect the clock edge and then sample your data such 
that the SPI timing is not violated.

Concerning the miso (your output) you'll do that based on the detected 
spi clock edge (rising and falling) as well. Here as well the required 
timing needs to be fulfilled.

With these facts given, you can easily determine whether 10x 
oversampling is sufficient. Check the allowed minimal (clk) pulse width 
as well (I it's not 50/50, this can have an impact on the requirement as 
well).

Author: Lothar Miller (lkmiller) (Moderator)
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SparkyT wrote:
> I am writing an FSM based SPI slave for mode 0,0 in a FPGA.
Id did also, have a look at it:
Beitrag "Re: Erfahrung mit SPI Slave und Spartan 6 FPGA?"

> Because of a different error, I cant run (so far) a post layout
> simulation to see timmings (will do though).
I didn't a timing simulation since last millenium: its not neccessary 
when you do a synchronous design and you have correct constraints...

> pre-synth and post-synth simulation show correct behaviour,
Do you have a correct model of the "outside world"?

> but finally trying on real hw, it fails.
How do you see that? What is going wrong and what do you expect instead?

Author: SparkyT (Guest)
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Hi, thanks for the replies,

no, i did not have a correct model of the outside world!

pol 0 and pha 0, to me ( and i guess to the rest of the world) it meant 
that data are captured on the clock's rising edge and data is propagated 
on a falling edge .

BUT for the TI cpu we use, it means that data is propagated on a rising 
edge and sampled at the falling edge! talk about confusion!

which means i have to go back to my code and adapt to these new facts...

thanks for your time, and if (or when!)  i get into trouble i will ask 
for your help.

thanks again

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