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Forum: FPGA, VHDL & Verilog put attributes into file possible?


von spyro (Guest)


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Hello everyone,

I am having a huge list of attributes being comprised of KEEP, 
DONT_TOUCH and MARK_DEBUG. It's mainly the list of signals I want to 
debug within my design. Since the list takes up so much space I was 
wondering if it's possible to somehow store all those attributes within 
a file and load them into my VHDL-design depending on a global 
constant-variable/signal/whatever?

So it would look something like this:
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entity top is
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end top ;
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architecture Behavioral of top is
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    if(DEBUG_ENABLE = "TRUE") then
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        include "../path/to/file.txt";
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    end if;
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begin
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end Behavioral;

and the file would look something like this:
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    attribute KEEP          : string;
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    attribute DONT_TOUCH    : string;
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    attribute MARK_DEBUG    : string;
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    attribute KEEP of signal_1            : signal is "TRUE";
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    attribute KEEP of signal_1            : signal is "TRUE";
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    attribute DONT_TOUCH of signal_1      : signal is "TRUE";
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    attribute DONT_TOUCH of signal_1      : signal is "TRUE";
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    attribute MARK_DEBUG of signal_1      : signal is "TRUE";
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    attribute MARK_DEBUG of signal_1      : signal is "TRUE";

Anyone knows, whether that is possible?

Cheers,
Spyro

von spyro (Guest)


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For anyone who might be interested on the topic.
Here is the stackoverflow link with some possibilities on how to 
approach this, although there seems not to exist a fitting solution to 
my request.

http://stackoverflow.com/questions/30862986/put-attributes-into-file-possible

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