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Forum: FPGA, VHDL & Verilog Using Special characters in Module name


Author: Anil (Guest)
Posted on:

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hi,
I have to use special character & in the module name and I have named 
the file name same as module name (added space at the end of the module 
name).
I wasn't able to compile, looks like vcs is not accepting space in the 
file name :

------------------
module \&abc_123 ;
integer \&$$abc ;
initial begin
\&$$abc =20;
$display("&$$abc =%d",\&$$abc );
#10 $finish;
end
 endmodule
-------------

Did I miss anything? Any help Please.

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