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Forum: FPGA, VHDL & Verilog Describe in VHDL a generator parallel 4 bits to serial 1 bit


Author: issam sassi (Company: uqtr) (isamel85)
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Hello,
I want to describe in VHDL a generator parallel 4 bits to serial 1 bit.
Indeed, at each clock edge (250 kHz), we take only one bit starting with 
the least significant bit (LSB).
Example:
Input = "0101" (over 4 bits)
So at first clock edge, output = '1' (LSB)
Second clock edge, output = '0'
Third clock edge, output = '1'
Fourth clock edge, output = '0' (MSB)
There's someone there who can help me?
And thank you

Author: Lothar Miller (lkmiller) (Moderator)
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issam sassi wrote:
> There's someone there who can help me?
You should have a look for a preloadable shift register.

Indeed your exercise is do simple, that it will loosely fit in 10 lines 
of VHDL code...

issam sassi wrote:
> There's someone there who can help me?
Some questions should be answered before:
Where's the clock coming from? Are there only and exactly 4 clock edges? 
How may the shift register know, that there is new data ready to be 
transmitted?

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