Forum: FPGA, VHDL & Verilog VHDL : 4-Bit Adder and Subtractor Problem

Author: Mahmood Mehri (mahmood_m)
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i have some trouble with designing an 4-bit adder and subtracter in VHDL
i posted in stackoverflow about my problem , but no answer yet !
the post is here , with codes , image and notes :

help me solve that problems

Author: matthias (Guest)
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I didn't checked if the algorithm itself is correct, but in your 
testbench for example the signal 'sum'& 'E' isn't in the sensitivity 
list. All signals that can change and are on the right side or in an 
if-comparison etc must be listed in the sensitivity list to ensure that 
the Simulator can calculate the new signals.


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