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Forum: FPGA, VHDL & Verilog M9K memory block issue in Cyclone IV


Author: jeorges FrenchRivera (Company: xlue) (khal1985)
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Hi,

I'm trying to use the M9K memory block of my FPGA cyclone IV.
For that purpose I use the Mega-wizard of Quartus II 10.1sp1 Web 
Edition.
I implemented the 1 port RAM with single clock, the entity generated 
looks like the code below:
  entity RAM_1Port IS
PORT
  (
    address  : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
    clock    : IN STD_LOGIC  := '1';
    data    : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
    wren    : IN STD_LOGIC ;
    q      : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
  );
END RAM_1Port ; 
.
To test this memory, i have created the code below:
-- Instantiate the RAM single port mode 
RAM1: RAM_1Port port map(RAM_address,CLOCK_50,RAM_data_IN,RAM_wren,Output_RAM);
  
test: process(CLOCK_50,KEY) -- asynchonos process 
   begin  
    
     IF (KEY='0') THEN        -- when reset is selected 

       -- init signals RAM Single port 
       wr_address <=(others => '0');
       RAM_address<=(others =>'0');
       RAM_data_IN<=(others =>'0');
       RAM_wren<='0';
       Write_Ok<='0';
     ELSIF(rising_edge(CLOCK_50)) then 
    
        if(Write_Ok='0') then  -- start writing 
        
        RAM_wren<='1';

        RAM_address<=std_logic_vector(to_unsigned(10, 5));  
        RAM_data_IN<=std_logic_vector(to_unsigned(1984, 16));
        cpt<=cpt+1;
         
        if(cpt=1) then 
          Write_Ok<='1';
          cpt<=0;
        end if;
       end if;

       if(Write_Ok='1') then  --start reading 

        RAM_wren<='0';
        RAM_address<=std_logic_vector(to_unsigned(10, 5));
        cpt<=cpt+1;   
        RAM_out<=Output_RAM;
        
        if(cpt=1) then 
          Write_Ok<='0';
          cpt<=0;
        end if;
      end if;
   end if;
 end process;    
END;
The problem i have is that the output RAM_out is always zero, i don't 
understand why.
Can you help on this please if you have an idea?
Best regards

Author: P. K. (pek)
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I'd observe the signals "cpt" and "Write_ok" in the Simulator (anyway, 
observe them all, so you'll learn what's going on, and what is possibly 
not solved very good in your test module).

From the code, it's not clear, what "cpt" is, and how it has been 
initialzed. If it's not 0 or 1 at start, you'll end up with Trouble 
(e.g. if ist value is -37 or 2). Anyway, ist not quite clear to me what 
this "cpt" is good for...

: Edited by User
Author: jeorges FrenchRivera (Company: xlue) (khal1985)
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Thanks you pek for your answer. cpt is integer range 0 to 15 and 
initialized zero, i used it because in the beginning i have a loop of 16 
iterations.
Now, i remove the cpt from my code and I always have the same problem.
You find enclosed a screenshot of my signals.
Best regards

Author: P. K. (pek)
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If SignalTap shows signals in red they are (in case of a bus sometimes 
partially, so open it to see more) not available (after synthesis).

So check why those (red marked) signals where synthesized away. Make an 
interpretation of the warnings Quartus issues.

Author: jeorges FrenchRivera (Company: xlue) (khal1985)
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I did not pay attention to red signals thinks.
I have this warning concerning the output but i don't understand:
Warning (14320): Synthesized away node 
"RAM_1Port:RAM1|altsyncram:altsyncram_component|altsyncram_hci1:auto_gen 
erated|q_a[0]".
How can I resolve this warning ?
Best regards

Author: P. K. (pek)
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That means as much as "your RAM output is never assigned". In other 
words, your code is erroneous. Time to set up a simulation (the thing 
you do BEFORE synthesis) with all signals displayed...

Author: jeorges FrenchRivera (Company: xlue) (khal1985)
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It's very strange when i assign RAM output to LED(mapped to the leds in 
the board) the warning disappear but when it assigned to a an internal 
signal there is a warning.
Any case i can't exploit the output of this RAM.
I don't know what going with the magafuntions of altera, never work for 
me.
Best regards

Author: P. K. (pek)
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jeorges FrenchRivera wrote:
> I don't know what going with the magafuntions of altera, never work for
> me.

I think it's useless to blame the mega function. Start to simulate your 
design and display _ALL_ your signals to learn what happens.

Author: jeorges FrenchRivera (Company: xlue) (khal1985)
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You are right pek,it's unless to blame the mega function.
I simulated as you suggested and it works. But with quartus and using 
the signal tap, i still have Zero in the output of the RAM.
Best regards

Author: P. K. (pek)
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You should look out for the warning

> Warning (14284): Synthesized away the following node(s):

And investigate what it says. Even when observing with SignalTap, the 
synthesizer throws unused logic (not having influence on any outputs) 
away. To maintain the function, attach the outputs to any unused output 
pin of the FPGA and observe again.

Author: jeorges FrenchRivera (Company: xlue) (khal1985)
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I don't have the
> Warning (14284): Synthesized away the following node(s): because i connected as 
you suggested the output to the LED in my board, in the same time i can see that 
it works. But, when this output is connected to a global signal, its value is 
always zero.  It's normal ?
Best regards

Author: P. K. (pek)
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jeorges FrenchRivera wrote:
> But, when this output is connected to a global signal, its value is
> always zero.  It's normal ?

If the global signal leads to nowhere, the answer is yes. Even a 
"global" signal that does not drive any output has no function and 
therefore may be taken out of the design by optimisation.

The fact that a SignalTap logging is not considered as an "output" and 
the logic is optimized away anyway is a little nuisance but you can deal 
with: As soon as signals either are registered or going through the 
interface of a (sub)-entity you will be able to observe them with 
SignalTap (however, they will be optimized away anyway as soon as you 
switch of SignalTap, as they still have no influence on any output).

Author: jeorges FrenchRivera (Company: xlue) (khal1985)
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thank you very much Pek for your help. Have a good day.
Best regards

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