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Forum: FPGA, VHDL & Verilog How to generate random delay in "generate" loop?


von RandomDelay (Guest)


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Hi,
How can I generate random time delay in following code? What I found so 
far is only random generation in a process with function "uniform". I 
want to generate random time delays during compile time. Is it possible?

Thanks.
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  for i in 0 to nr_entries-1 generate    
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    multiple_n: w_entity 
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      generic map (delay => (i+1) * 1 ps , chain_len => nr_chains) -- Delay must be "random" from 100 to 300 ps
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      port map (
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        rst_i => s_rst,
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        out_o => s_inp(i)
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      );
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  end generate;

I am now generating it from for-variable "i" which is not random.

von Andreas (Guest)


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Did you have an Idea, how the syntesizer should release such random 
delay time?

Best Regards

von bogomil (Guest)


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i suggest this is for Simulation only anyway

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