Forum: FPGA, VHDL & Verilog Creation of regions with Floorplanning( LiberoSOC)

Author: Mars (Guest)
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I'm using an FPGA of Microsemi, I use LiberoSOC to create projects.
I ask if there are an opportunity to specify the regions of logic module 
that will be used in the project. This is possible manually but is it 
possible using Tcl scripts?



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