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Forum: FPGA, VHDL & Verilog Decoder 3:8 simulation with out test bench


Decoder 3:8 simulation with out test bench
von Sayeed (Guest)

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Hi

I need a help to simulate decode  VHDL core in ISIM.

Regards
Sayeed

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Re: Decoder 3:8 simulation with out test bench
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Sayeed wrote:
> I need a help to simulate decode  VHDL core in ISIM.
And what is your actual problem? How far do you get? And what problems 
do you encounter? What is your specific 3:8 decoder doing? And how 
does your decoder "core" look like?

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Re: Decoder 3:8 simulation with out test bench
von alexinho (Guest)

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Please do not delet that!

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