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Forum: FPGA, VHDL & Verilog verilog error


Author: Ahmadsyazwan Syazwan (syazwan)
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module controlunit control_path 
(opcode,outA,carry,reset,pc_sel,pc_wrt,addr_sel,
ir_wrt,data_sel,rega_sel,
reg_wrt,opb_sel,opa_sel,
alu_sel,re,we,clk);


 Error (10170): Verilog HDL syntax error at controlunit.v(3) near text 
"control_path";  expecting ";"

please help me solve this error.

: Edited by User

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