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Forum: FPGA, VHDL & Verilog How to call function on case statement (Verilog)?


Author: Monlak U. (monlak_u)
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module Counter(
input up,
input down,
input open,
input openHold,
input close,
input clk_in25mhz,
input clk_in1hz,
output reg DoorOpen,
output reg UpStatus,
output reg DownStatus,
output reg propeOut
);
reg rst3s;
reg rst2s;
reg PropeResult3s,PropeResult2s;

always @ (up or down or open or openHold or close or clk_in25mhz
or clk_in1hz
or rst3s
or rst2s
or PropeResult3s or PropeResult2s)
begin
case ({down,up,open})
3 b000 : begin
propeOut <= clk_in25mhz; DoorOpen <= 1 b0; UpStatus <= 1 b0; DownStatus 
<= 1 b0;
rst2s <= 1 b1; rst3s <= 1 b1;
end
3 b001 : begin
rst3s <= 1 b1;
if (openHold) begin
DoorOpen = 1 b1;
propeOut <= 1 b0;
UpStatus <= 1 b0;
DownStatus <= 1 b0;
end
else if (close) begin
DoorOpen <= 1 b0;
propeOut <= 1 b1;
UpStatus <= 1 b0;
DownStatus <= 1 b0;
end
else
begin
rst2s <= 1 b1;
DoorOpen <= 1 b1; UpStatus <= 1 b0; DownStatus <= 1 b0; propeOut <= 
PropeResult2s;
end
end

3 b010 : begin
rst3s <= 1 b1;
DoorOpen <= 1 b0; UpStatus <= 1 b1; DownStatus <= 1 b0; propeOut <= 
PropeResult3s;
end
3 b100 : begin
rst3s <= 1 b0;
DoorOpen <= 1 b0; UpStatus <= 1 b0; DownStatus <= 1 b1; propeOut <= 
PropeResult3s;
end
endcase
end

counter3sec CupDown(clk_in1hz,rst3s,PropeResult3s);
counter2sec Copen(clk_in1hz,rst2s,PropeResult2s);

the result of PropeResult3s and PropeResult2s is always x as capture 
image

Author: mhm (Guest)
Posted on:

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Monlak U. wrote:
> ...

Well, how do you think someone can help you with this formatting? Such 
long codes have to be posted as attachment!

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