Forum: FPGA, VHDL & Verilog Routing limits in fpga design

Author: henry (Guest)
Posted on:

Rate this post
0 useful
not useful
Hello. I need to connect any of n inputs to any of n outputs (crossbar 
What design considerations should I care about, in choosing an fpga for 
a given n?
Please consider that speed is in the tens of MHz, power consumption 
doesn't care and non-blocking switch is not required

Just for example, on digikey I see a low cost lattice ice40HX1K with 96 
i/o ports and 1280 logic units. How big my n could be in this case?


Author: Andi M. (andi6510)
Posted on:

Rate this post
0 useful
not useful
I would say for a simple switching function the number of IO pins is the 
limiting factor.

You'll need:
N inputs
N outputs
X lines for control, reset, clock

for very small FPGAs the number of logic units (LU) can also become a 
limiting factor. What a single LU actually can do depends strongly on 
the device type. But in worst case it is equivalent to a single one-bit 
2 to 1 mux. So you would roughly need 0.5*N*N LUs to do the job. But 
many FPGAs have special muxing features that simplify your special task 
and reduce the number of LUs required.

The only reliable way to find out if a design fits into a device is to 
actually try it by running a complete design process until the final 
binary file is created. This can be done without purchasing a device - 
"just" download the vendor's development toolchain, enter your design 
and run the compile and synthesis steps. As a result you will get a 
detailed report of how many resources in the device have been used. If 
only a small percentage of the device's resources is used a smaller 
device can be selected. If the design does not fit select a bigger 
device and restart the process.

Author: henry (Guest)
Posted on:

Rate this post
0 useful
not useful
Thanks, Andi, I'll follow your advice.
Last time I used fpga was with the Altera tool chain, 4 years ago 
(perhaps more). This time I'm gonna try SystemC instead of Verilog



Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.