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Forum: FPGA, VHDL & Verilog Looking to understand intra assignment delays


Author: mavericknik (Guest)
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Hi,

I'm learning verilog and looking to understand intra assignment delays. 
I read some books and I think I have the basics covered. I was looking 
online for some questions and came across this which I cant seem to 
understand:


Q: Using the given, draw the waveforms for the following
versions of a (each version is separate, i.e. not in the same run):



reg clk;
reg a;

always #10 clk = ~clk;

(1) always @(clk) a = #5  clk;
(2) always @(clk) a = #10 clk;
(3) always @(clk) a = #15 clk;

Now, change a to wire, and draw for:

(4) assign #5  a = clk;
(5) assign #10 a = clk;
(6) assign #15 a = clk;

A:


       10      30      50      70      90     110     130
        __     ___     ___     ___     ___     ___     __
clk ___|   |___|   |___|   |___|   |___|   |___|   |___|   |___

          __     ___     ___     ___     ___     ___     __
(1)a ____|   |___|   |___|   |___|   |___|   |___|   |___|   |_

            __     ___     ___     ___     ___     ___     __
(2)a ______|   |___|   |___|   |___|   |___|   |___|   |___|


(3)a ________________________________________________________

Since the #delay cancels future events when it activates, any delay
over the actual 1/2 period time of the clk flatlines...

With changing a to a wire and using assign, we
just accomplish the same thing...

       10      30      50      70      90     110     130
        __     ___     ___     ___     ___     ___     __
clk ___|   |___|   |___|   |___|   |___|   |___|   |___|   |___

          __     ___     ___     ___     ___     ___     __
(4)a ____|   |___|   |___|   |___|   |___|   |___|   |___|   |_

            __     ___     ___     ___     ___     ___     __
(5)a ______|   |___|   |___|   |___|   |___|   |___|   |___|


(6)a ________________________________________________________




For each of the #15 delays, how is the output a always 0? The text 
states the #delay cancels future events when it activates. What does 
this mean? Shouldnt a be assigned 1 #15 after the clock every time?

Thanks

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