Forum: FPGA, VHDL & Verilog Asynchronous mutex and arbiter

Author: Charles Effiong (icharles)
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1. Does anyone knows a gate level implementation of asynchronous 
metastability filter for mutex ? I couldn't find a gate level 
description online.

2. I created a MUTEX using two NAND gate. See attached file pls

After running simulation, the output G1, G2 is 'U' :( If I change one of 
R1,R2 to be '0' it works. What could be wrong ?

3. Does anyone knows how to code an asynchronous arbiter that can be 
used to control a MUX or demux. I'm did the coding but have some 
problems simulating it.

Any help or reference materials would be appreciated. Thanks

: Edited by User
Author: Lothar Miller (lkmiller) (Moderator)
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Pls use the VHDL tags further on. It will give you and us neat syntax 
wait for clock_cycle; 
R1 <= '1'; 
wait for clock_cycle; 
R2 <= '1'; 

> Interface is as below:
And the implementation?

> After running simulation
Which one?

> What could be wrong ?
Something with the code not posted here...


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