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Forum: FPGA, VHDL & Verilog Ring Oscilator in VHDL


Author: RO (Guest)
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Hi,
I am trying to implement a Ring Oscilator on FPGA. First, I want to 
simulate it to "see" a working code, then I will flash it on an FPGA 
board, therefore I don't want to use "wait for.." statements in code. 
The purpose is to make a physically unclonable function.
I am receiving simulation error during simulation:

ERROR: at 100 ns(10000): Iteration limit 10000 is reached. Possible zero 
delay oscillation detected where simulation can not advance in time 
because signals can not resolve to a stable value in File "....vhd" Line 
45. Please correct this code in order to advance past the current 
simulation time.

Can anoybody help me?
Maybe, is it because of optimization? How can I avoid optimization?

Thanks.
ISE WebPACK 14.7
Win 7 32-bit

source code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ro_puf is
    Port ( clk_i : in  STD_LOGIC;
           rst_i : in  STD_LOGIC;
        clk_o : buffer  STD_LOGIC);
end ro_puf;

architecture Behavioral of ro_puf is
  signal chain :std_logic_vector(30 downto 0);
  attribute syn_keep: boolean;
  attribute syn_keep of chain: signal is true;
begin
  gen_chain:
  for i in 1 to 30 generate
    chain(i) <= not chain(i-1);
  end generate;
  chain(0) <= not chain(30) or not rst_i;

t_FF: process(rst_i, chain(0))
  begin
    if rst_i = '0' then
      clk_o <= '0';
    elsif rising_edge(chain(0)) then
      clk_o <= not clk_o;
    end if;
  end process t_FF;

end Behavioral;

Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY ro_tb IS
END ro_tb;
 
ARCHITECTURE behavior OF ro_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ro_puf
    PORT(
         clk_i : IN  std_logic;
         rst_i : IN  std_logic;
         clk_o : BUFFER  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk_i : std_logic := '0';
   signal rst_i : std_logic := '0';

   --Outputs
   signal clk_o : std_logic;

   -- Clock period definitions
   constant clk_i_period : time := 10 ns;
 --  constant clk_o_period : time := 10 ns;
 
BEGIN
 
  -- Instantiate the Unit Under Test (UUT)
   uut: ro_puf PORT MAP (
          clk_i => clk_i,
          rst_i => rst_i,
          clk_o => clk_o
        );

   -- Clock process definitions
   clk_i_process :process
   begin
    clk_i <= '0';
    wait for clk_i_period/2;
    clk_i <= '1';
    wait for clk_i_period/2;
   end process;
 
--   clk_o_process :process
--   begin
--    clk_o <= '0';
--    wait for clk_o_period/2;
--    clk_o <= '1';
--    wait for clk_o_period/2;
--   end process;
-- 

   -- Stimulus process
   stim_proc: process
   begin    
      -- hold reset state for 100 ns.
      wait for 100 ns;  
    rst_i <= '1';
    wait for 50 ns;
    rst_i <= '0';
      wait for clk_i_period*100;

      -- insert stimulus here 

      wait;
   end process;

END;

Author: Lattice User (Guest)
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RO wrote:

> Maybe, is it because of optimization?

This is not the cause.

A ringoscillator is based on non zero delay of your inverters. The 
functional simulation however doesn't know about the delay, and 
therefore it gets caught in an infinite loop.

You need to run a post P&R simulation for to see it working.


> The purpose is to make a physically unclonable function.

I doubt you will achieve that, as the variation accross temperature and 
power supply are probably larger than the differences between individual 
FPGAs.

The jitter of such a ring oscillator is also often used as an TRNG.

Author: Jürgen Schuhmacher (engineer)
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You will need to implement a signal stucture, where an inverter acts as 
a delay and loop it back to the input. In order to make this work, an 
inverter chain will be required and it will have to be implemented in 
low level language in order to prevent the tool from removing logic.

You should only make use of waits in order to simulate physical delay 
with some 20...30ps between the inverters (LUTs) to get an impression of 
the function.

No clocking will be needed. Instead intelligent buffering is required to 
shape a useable clock from out of an oscillating ring:

http://www.96khz.org/oldpages/digitalnoisegenerator.htm

Author: Jürgen Schuhmacher (engineer)
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A, I just have seen, there was somebody posting the same time, ok.

Lattice User wrote:
> The jitter of such a ring oscillator is also often used as an TRNG.
Whereby it has to be mentioned, that the jitter is pretty low and 
moreovere these circuits appear to synchronize their behaviour on 
existent clocks in an FPGA because of power switching. Therefore I am 
continuosly changing the frequency in my solution to avoid the issue.

: Edited by User
Author: Lothar Miller (lkmiller) (Moderator)
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RO wrote:
> Can anoybody help me?
> Maybe, is it because of optimization? How can I avoid optimization?
No its only because your code does not implement any delay which is 
necessary for a ring oscillator. Therefore the simulator calculates 
results but never is able to increase the time step. Try this:
  gen_chain:
  for i in 1 to 30 generate
    chain(i) <= not chain(i-1) after 200 ps;
  end generate;
  chain(0) <= not chain(30) or not rst_i  after 200 ps;

Have a look at this (try with google Translator, its German):
http://www.lothar-miller.de/s9y/archives/90-Ringos...
http://www.lothar-miller.de/s9y/archives/35-Ringos...

: Edited by Moderator
Author: RO (Guest)
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Ok, thanks for  the answers.
I will try them.

Author: Dogbert (Guest)
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Lattice User wrote:
> I doubt you will achieve that, as the variation accross temperature and
> power supply are probably larger than the differences between individual
> FPGAs.

http://www.ee.usyd.edu.au/people/philip.leong/User...

Author: FPGA-Freak (Guest)
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Chip Identification by analyzing ring oscillators? Not very secure, or?

Author: Duke Scarring (Guest)
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PUFs[1] on FPGA are just for academic intrest...

[1] https://en.wikipedia.org/wiki/Physical_unclonable_function

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