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Forum: FPGA, VHDL & Verilog Multiple DDR3 Controllers in Stratix V


Author: Antony Mathew (antony_mat)
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Hi guys i am trying to implement 2 DDR3 controllers (independent 
controllers without any pll/dll/oct sharing) inside a stratix 5 device.
I use Qsys to generate the system with  PCIe Hard IP and DMA Ipcores.

What i come across is a OCT related error as below link, which altera
says as a software issue.

https://www.altera.com/support/support-resources/k...

But for me solution in above page not working. I am using quartus tool 
ver 14.1

All example projects from altera seems to be shared DDR3 memory 
controllers, which is not what i require.

Any idea guys ??
Thanks in advance...

Author: guest (Guest)
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mhm from what I remember there are multiple configurations for the OCT 
pin in the DDR3 controllers
you can set it to OCT master or slave, you'll have to make one of your 
controllers a slave and connect it to the master's OCT output
the problem seems to be that you can't directly share the pin, which is 
kind of analog stuff anyways, it's connected to a resistor on your PCB 
and supposed to measure it's value in order to match the internal DDR3 
termination resistor value...

Author: Antony Mathew (antony_mat)
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guest wrote:
> mhm from what I remember there are multiple configurations for the OCT
> pin in the DDR3 controllers
> you can set it to OCT master or slave, you'll have to make one of your
> controllers a slave and connect it to the master's OCT output
> the problem seems to be that you can't directly share the pin, which is
> kind of analog stuff anyways, it's connected to a resistor on your PCB
> and supposed to measure it's value in order to match the internal DDR3
> termination resistor value...

okie.. i will try in that direction.
All sample projects of altera with shared ddr3 controllers use OCT 
sharing. I thought since i am using an independend configuration, 
sharing is not required.

Author: dedomrak (Guest)
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hi Mathew
I got the same error when tried to merge 2 DDR3 + 2 RLDRAM memory 
controllers in one S5 device. The problem was in RZQ sharing - I had
only 3 OCT resistors on board - 2 for each DDR and 1 shared for RLDRAM.
This particular error was emerged from next rows in my QSF file-
   set_instance_assignment -name TERMINATION_CONTROL_BLOCK 
"RLDRAM2_Controller:CBank2|RLDRAM2_Bank0_example_if0:if0|altera_mem_if_o 
ct_stratixv:oct0|sd1a_0"  -to mem_qk2[0] -tag 
__RLDRAM2_Bank0_example_if0_p0
set_instance_assignment -name TERMINATION_CONTROL_BLOCK 
"RLDRAM2_Controller:CBank2|RLDRAM2_Bank0_example_if0:if0|altera_mem_if_o 
ct_stratixv:oct0|sd1a_0"  -to mem_qk2[1] -tag 
__RLDRAM2_Bank0_example_if0_p0
set_instance_assignment -name TERMINATION_CONTROL_BLOCK 
"RLDRAM2_Controller:CBank2|RLDRAM2_Bank0_example_if0:if0|altera_mem_if_o 
ct_stratixv:oct0|sd1a_0"  -to mem_qk_n2[0] -tag 
__RLDRAM2_Bank0_example_if0_p0
set_instance_assignment -name TERMINATION_CONTROL_BLOCK 
"RLDRAM2_Controller:CBank2|RLDRAM2_Bank0_example_if0:if0|altera_mem_if_o 
ct_stratixv:oct0|sd1a_0"  -to mem_qk_n2[1] -tag 
__RLDRAM2_Bank0_example_if0_p0

Did you have anything in your QSF >
If manually edit this file you may missed this rows.

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