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Forum: FPGA, VHDL & Verilog Test bench I2C (vhdl)


Author: Javier PA (lascameador)
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hi guys!
I've developed two i2c components.
u1: SlaveI2CA generic map (SLAVE_ADDR) port map(scl,sda1,clk,rst,starting1,sda2);
u2: SlaveI2CB generic map (SLAVE_ADDR) port map(scl,sda3,clk,rst,starting2,sda4);

I want to connect sda2 and sda3 with a pullup resistor (in simulation) 
but i don't know how to do this.
When I write 'Z' or '0' the slave works,while it has already been 
programmed ,but i don't know how to develope this function in 
simulation.

any advices??
thanks ;)

Author: Lothar Miller (lkmiller) (Moderator)
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Javier PA wrote:
> but i don't know how to develope this function in simulation.
Try it with Google translator:
http://www.lothar-miller.de/s9y/archives/91-Schalt...

I would take the switch model and connect it with a pullup (='H') this 
way:
 SDA_A --- Switch --- 'H' --- Switch --- SDA_B

 SCL_A --- Switch --- 'H' --- Switch --- SCL_B

Of course the switch model could be simplified to a Zero-Ohm this way:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity zeroohm is
    Port ( A : inout  STD_LOGIC;
           B : inout  STD_LOGIC);
end swbidi;

architecture Behavioral of zeroohm is
begin
  process
    variable thentime : time;
  begin
    wait on A, B until thentime /= now;
    
    -- Break
    thentime := now;
    A <= 'Z';
    B <= 'Z';
    wait for 0 ns;
    
    -- Make
    A <= B;
    B <= A;
  end process;

end Behavioral;

: Edited by Moderator

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