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Forum: FPGA, VHDL & Verilog help with vhdl code


Author: Ben Nguyen (onecabwonder)
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Design a component that uses a 4-to-1 multiplexer to choose between one 
of four different operations
to get the result from. Each of the operations and the multiplexer 
should be behavioral design in their
own modules / files to be used in the overall component design as 
separate components. The
component being design must use structural design to provide the inputs 
to the components along with
getting their results.
The four operations expected are as follows:
- AND -- when selection bits are 00
- OR – when selection bits are 01
- XOR – when selection bits are 10
- NOT – when selection bits are 11
Each module is responsible for only 1 operation, so there should be a 
total of five different modules /
components including the multiplexer being used in the overall component 
design. Whenever a new
operation is selected or new inputs are provided to change the output of 
the operations the multiplexer
should determine its new output.
Each of the operations can be assumed to only require two inputs, each 1 
bit, to do the operations
except for the NOT operation, you can choose which input you want to 
invert the logic of. The overall
component design should have two inputs, selections bits and an output. 
Every gate in the design
should have a 3 ns delay, while NOT gates should have no delay.







this is my vhdl code and it seems to have errors but i dontknow what 
they are and if u can give me any feedback that is fine




thank you

: Edited by User
Author: Lothar Miller (lkmiller) (Moderator)
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>>> wholedesign.txt <<<
My VHDL designs end not with txt but with VHD or VHDL...

Ben Nguyen wrote:
> Every gate in the design should have a 3 ns delay
Please tell your teacher that this is a STUPID task. In a functional 
description no symbolic delays should be used.

Ben Nguyen wrote:
> this is my vhdl code and it seems to have errors but i dontknow what
> they are
But maybe, you can at least tell US what the toolchain (btw: which one?) 
tells YOU? Or should we find that out on our own?

Ben Nguyen wrote:
> so there should be a total of five different modules/components
> including the multiplexer
If this is the exercise, then why do you have 6 modules?
I think this two should be one and the same:
entity strct is

entity mxer is
But your design is nearly unreadable due to lack of any indention in 
your code...

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