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Forum: FPGA, VHDL & Verilog Designing an Audio Processor verilog/FPGA


Author: Ashkan Markus (Company: IKIU) (spartanyjm)
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hi, this project is meant to implement a guitar multieffect pedal.
The code here is the top module. the other submodules all check syntax 
green and even the top module does not give any errors,just warnings. 
but even that is concerning. I've consulted a lot with an FPGA expert. 
but I'd like to share it with you too. the code & the warnings I get are 
as below :
module Multieffect(din1,Audio_out,Clk1,control,Reset,rsta,wea);
input din1;
input Clk1,Reset,wea;
input [1:0]control;
input rsta;
output Audio_out;
reg [11:0]t1;
reg [11:0]t2,t3,REG_0;
wire clkdv;
wire Clk2x;
wire [11:0]SIPORAM,CROMMUX,PROMMUX,ECHOREG,MUXRAM,RAMREG,REG0,REGD,ADDED_AUDIO,SUB_AUDIO,muxtoPISO;
wire clk0;
reg [11:0]ADDRESS;
integer k=0;
assign ECHOREG=1000;
always @(posedge clkdv)
begin
if (k==4094)
ADDRESS <=0;
else
ADDRESS <= ADDRESS + 1'b1 ;
k<=k+1;
end 


dcm1 u(.CLKIN_IN(Clk1),.RST_IN(Reset),.CLKDV_OUT(clkdv),.CLKIN_IBUFG_OUT(),.CLK0_OUT(clk0),.CLK2X_OUT(Clk2x),.LOCKED_OUT());
SIPO u0(.din(din1),.clk(clkdv),.reset(Reset),.dout(SIPORAM));
CHORUSROM u1(.out(CROMMUX),.clk(Clk2x));
PHASERROM u2(.out(PROMMUX),.clk(Clk2x));
mux4_1 u3(.din_0(ECHOREG),.din_1(CROMMUX),.din_2(PROMMUX),.din_3(PROMMUX),.sel(control),.mux_out(MUXRAM));
SDP_BRAM u4(.clka(clkdv),.wea(wea),.addra(ADDRESS),.dina(SIPORAM),.clkb(Clk2x),.rstb(rsta),.addrb(MUXRAM),.doutb(RAMREG));


AddSub u5 (.clk(clk0),.ce(1'b1),.s(ADDED_AUDIO),.a(RAMREG),.b(RAMREG));
AddSub2 u6 (.clk(clk0),.ce(1'b1),.s(SUB_AUDIO),.a(RAMREG),.b(RAMREG));
mux_4_1_2 u7(.in10(ADDED_AUDIO),.in11(ADDED_AUDIO),.in12(ADDED_AUDIO),.in13(SUB_AUDIO),.sel1(control),.mux_out1(muxtoPISO));
PISO u8(.clk(clk0),.ld(1'b1),.shift(1'b1),.pi(muxtoPISO),.q(Audio_out));

endmodule



WARNING:HDLCompiler:1499 - "C:\Users\YJM\Multi.effect\SDP_BRAM.v" Line 
39: Empty module <SDP_BRAM> remains a black box.
WARNING:Xst:2999 - Signal 'Mem', unconnected in block 'CHORUSROM', is 
tied to its initial value.
WARNING:Xst:3035 - Index value(s) does not match array range for signal 
<Mem>, simulation mismatch.
WARNING:Xst:2999 - Signal 'Mem1', unconnected in block 'PHASERROM', is 
tied to its initial value.
WARNING:Xst:3035 - Index value(s) does not match array range for signal 
<Mem1>, simulation mismatch.
WARNING:Xst:1290 - Hierarchical block <u7> is unconnected in block 
<Multieffect>.
   It will be removed from the design.
WARNING:Xst:1710 - FF/Latch <out_0> (without init value) has a constant 
value of 0 in block <PHASERROM>. This FF/Latch will be trimmed during 
the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <out_9> 
(without init value) has a constant value of 0 in block <PHASERROM>. 
This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <out_10> 
(without init value) has a constant value of 0 in block <PHASERROM>. 
This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <out_11> 
(without init value) has a constant value of 0 in block <PHASERROM>. 
This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1290 - Hierarchical block <u7> is unconnected in block 
<Multieffect>.
   It will be removed from the design.




Now what do you guys see ? why is <u7> removed from the design ?

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