I have this Verilog project but I don't know how to start with it, or
how to do the test bench
Any help is appreciated!
Design a 1-bit expandable magnitude comparator that can be used as shown
in the pic attached.
The 1-bit expandable comparator accepts an xi input bit and a yi input
bit along with gin and ein inputs (the result of the comparison of the
more significant bits of X and Y) and produces gout and eout outputs to
indicate that X is greater than or equal to Y.
Create a Verilog behavioral dataflow model of the 1-bit comparator using
a propagation delay of 10ns for both outputs. Verify your design with a
testbench that exhaustively generates all possible input stimulus
Once your 1-bit comparator is correct, create a 4-bit comparator as
depicted above. Create a testbench to generate all possible inputs.
you can start with pseudo code and analyze the logic at first.
perhaps you see it, otherwise make a truth table and you receive:
g_out = x and not(y)
e_out = x and y
you also need a bigger truth table to take g_in and e_in in
g_out = (x and not(y)) or g_in
the rest is verilog Basic knowledge
Thank you Klakx
But I'm pretty new to Verilog and this is my 2nd project. I don't have
enough knowledge yet :).
I'd be thankful if anyone could help me more explaining the requirements
and any codes that helps me starting this.
John wrote:> Design a 1-bit expandable magnitude comparator that can be used as shown> in the pic attached.
Step 1 has absolutely nothing to do with any HDL: pick out one of
those comparators. It has 4 inputs and 2 outputs. Set up a truth table
for each of the outputs. When you have done this, then maybe one can
help you to transfer your truth table to Verilog...
As a little hint: the truth table for e out looks like this
ein gin x y eout
0 X X X 0 | previous stage is unequal --> total result is unequal
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 X X Error | not possible! input can't be greater and equal the same time
> Create a Verilog behavioral dataflow model of the 1-bit comparator using> a propagation delay of 10ns for both outputs.
What a stupid requirement. In real life you must never use a
"pseudo-delay" in a functional description. Or: try it and remember
guest wrote:> this project SUUUCKS!
Hmmmmm, let me say it this way: YOU wanted to become an electronics
engineer. And that here is a (fairly easy) job for this kind of
business. It will get much more difficult later on...
I really wasn't sure what do do with those inputs on the 1-bit
comparator... how would here be "equal or greater" (Gin, Ein) inputs
when there is no previous instance of the module?
I'm sorry but i'm very new to this, and I'm getting a little frantic
guest wrote:> I really wasn't sure what do do with those inputs
It was the same for me. I did not know anything about this project. Then
I started thinking...
> how would here be "equal or greater" (Gin, Ein) inputs when there is no> previous instance of the module?
Then the "previous" result is neither greater nor is it equal. So both
of them will be '0'.
Lothar Miller wrote:>> how would here be "equal or greater" (Gin, Ein) inputs when there is no>> previous instance of the module?> Then the "previous" result is neither greater nor is it equal. So both> of them will be '0'.
It should be set to equal, otherwise the end result can't be equal at
I realized that almost simultaneously as you posted it; Thank you SO
much for the confirmation!!
I'm thinking I need to redraw my truth table to account for all possible
combinations of ein and gin, then rewrite my boolean expressions