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Forum: FPGA, VHDL & Verilog creating and ALU in verilog


Author: Harman Litt (Guest)
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I was wondering if it were possible to have if statements as so for the 
ALU I am trying to build. I am passing values from a datapath test bench 
to a datapath, from the datapath into the ALU, and from the ALU back to 
the datapath. What i am trying to do is create a control unit which will 
only pass values through a certain component if the corresponding 
control_ALU is activated.

here is my verilog code :

module ALU (
 input en_ALU, clk_ALU,
input [31:0]  inputA, inputB, control_ALU,
output [31:0] resultc
);
wire [31:0] res_out;


always @(control_ALU)
begin
        if(control_ALU[1])  begin
    andLogic  andLogic_component(
                                            .dataA (inputA),
                                            .dataB(inputB) ,
                                            .resultA (res_out));
end



 if(control_ALU[2]) begin
negate m0(
.inputnegate    (inputA),
.resultnegate   (res_out)
);
    end
end

reg64bit z(.clk(clk_ALU) , .clr(clr), .enable(en_ALU), .inputd(res_out), 
.outputq(resultc));


endmodule

Author: vincent himpe (Guest)
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Here is how i typically make ALU. I've done a number of custom 
processors this way.  Note : Verilog 2001 syntax and i do make use of 
command scheduling as per the official Verilog spec ( very few people 
know/use scheduling but all synthesizers support it : Quartuse, ISe , 
Synopsys )
module mini_alu( input [31:0] a,b ,
                 input [7:0] opcode,
                 input reset,
                 output [31:0] x )

`define opcNOP    8'd0
`define opcAND    8'd1
`define opcOR     8'd1
`define opcBWANDa  8'd2
`define opcBWANDb  8'd2

.... other opcodes

always_comb(begin)
case (opcode)
    `opcNOP : output = 32'h0;
    `opcAND : output = a & b;
    `opcBWANDa : output = &a;
     ....

    default :  output = 32'b0;
endcase
if (reset) output <= 32'hDEADBEEF
end

endmodule;

Author: vincent himpe (Guest)
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vincent himpe wrote:

drat ! typo's fixed
> Here is how i typically make ALU. I've done a number of custom
> processors this way.  Note : Verilog 2001 syntax and i do make use of
> command scheduling as per the official Verilog spec ( very few people
> know/use scheduling but all synthesizers support it : Quartuse, ISe ,
> Synopsys )

module mini_alu( input [31:0] a,b ,
                  input [7:0] opcode,
                  input reset,
                  output [31:0] x )

 `define opcNOP    8'd0
 `define opcAND    8'd1
 `define opcOR     8'd2
 `define opcBWANDa  8'd3
 `define opcBWANDb  8'd4

 // .... other opcodes

> always_comb begin
 case (opcode)
     `opcNOP : output = 32'h0;
     `opcAND : output = a & b;
     `opcBWANDa : output = &a;
     // ....

     default :  output = 32'b0;
 endcase
 if (reset) output <= 32'hDEADBEEF
 end

 endmodule;
[/code]

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