EmbDev.net

Forum: FPGA, VHDL & Verilog Regarding parallel to serial converter


Author: Basavaraj H. (basavaraj_h)
Posted on:

Rate this post
0 useful
not useful
Hi i want parallel to serial converter code using shift register or 
counter in verilog with 8 bit input, clk and enable and single bit 
output..

Here i added code for parallel to serial conv this which i wrote but it 
is not showing exact output simulation... please send me code..

code:

module paralleltoserialconvnew(clk,en,din,sclk,se,sdout);
input clk;
input en;
input [7:0] din;
wire [7:0] din;
output sclk;
output se;
output [7:0]sdout;
reg [7:0] sdout;

reg [7:0]sr;
reg [7:0] cnt_reg;
assign sclk=clk;
assign se = en;

always @ (posedge clk)
begin
if(en == 1)
 begin
 sr[7:0] <= din[7:0];
 cnt_reg <= 7;
 sdout <= 1;
 end

 else if ((en == 0) && (cnt_reg !=0))
 begin
 sr[7:0] <= ({din[0],din[7:1]});
 cnt_reg <= cnt_reg-1;
 sdout <= din[7:1];
 end

 else if((en == 0) && (cnt_reg == 0))
 begin
 sr[7:0] <= din[7:1];
// sr[7:0] <= din[0];
 sdout <= sr[7:0];
 end
 else ;
 end

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.