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Forum: FPGA, VHDL & Verilog help with a vhdl calculator


help with a vhdl calculator
von Yair O. (Company: ipn) (yai)

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here i attach my program, it must multiply, add, subtract and compare 2 
numbers of 2bits. I have a problem it says that logic equation has to 
many terms on signal a_to_g(3).

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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USE IEEE.STD_LOGIC_UNSIGNED.ALL;

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USE IEEE.numeric_std.ALL;

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ENTITY calc is

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  Port (Num1: in Signed (1 downto 0);

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    Num2: in Signed (1 downto 0);

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    S:  in STD_LOGIC_VECTOR (1 downto 0);

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    a_to_g:out STD_LOGIC_VECTOR (6 downto 0));

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end calc;

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Architecture tris of calc is

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signal SUM:Signed (4 downto 0);

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signal RES:Signed (4 downto 0);

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signal MUL:Signed (4 downto 0);

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signal COM:Signed (4 downto 0);

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signal DISP : signed(4 downto 0);

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begin 

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process(Num1,Num2,S)

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  BEGIN

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  CASE S IS

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    WHEN "00"=>SUM<=resize(Num1,5)+Num2;

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     WHEN "01"=>RES<=resize(Num1,5)-Num2;

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    WHEN "10"=>

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    if Num1>Num2 then 

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    COM <= "11110";

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    elsif Num1<Num2 then

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    COM <= "11011";

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    else

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    COM <= "11010";

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  end if;

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    WHEN OTHERS=>MUL<=resize(Num1,3)*Num2;

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    END CASE;

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END PROCESS;

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PROCESS (S,SUM,RES,MUL,COM)

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BEGIN

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IF (S="00") THEN DISP<=SUM;

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ELSIF (S="01") THEN DISP<=RES;

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ELSIF (S="10") THEN DISP<=COM;

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ELSE DISP<=MUL;

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  END IF;

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    END PROCESS;  

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process (DISP)

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  begin

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    case DISP is

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  -- output numbers

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  when "00000"=> a_to_g <="0000001";  --0

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  when "00001"=> a_to_g <="1001111";  --1

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  when "00010"=> a_to_g <="0010010";  --2

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  when "00011"=> a_to_g <="0000110";  --3

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  when "00100"=> a_to_g <="1001100";  --4

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  when "00101"=> a_to_g <="0100100";  --5

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  when "00110"=> a_to_g <="0100000";  --6

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  when "00111"=> a_to_g <="0001101";  --7

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  when "01000"=> a_to_g <="0000000";  --8

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  when "01001"=> a_to_g <="0000100";  --9

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  -- output symbols

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  when "11010"=> a_to_g <="1000001";  --=

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  when "11011"=> a_to_g <="1001110";  --<

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  when "11110"=> a_to_g <="1111000";  -->

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  when others => a_to_g <="0000000";

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end case;

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  end process;

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end tris;


  


  




  

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    Re: help with a vhdl calculator
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Yair Orta wrote:
> it says
WHO is IT?

> it says that logic equation has to many terms on signal a_to_g(3).
Nothing more? With wich words?

> USE IEEE.STD_LOGIC_UNSIGNED.ALL;
> USE IEEE.numeric_std.ALL;
Never ever use both of them together!
Use the numeric_std solely. It has all the conversions you need. Try 
this with Google translator, its German:
http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

  


  




  

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