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Forum: FPGA, VHDL & Verilog help with a vhdl calculator


Author: Yair Orta (Company: ipn) (yai)
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here i attach my program, it must multiply, add, subtract and compare 2 
numbers of 2bits. I have a problem it says that logic equation has to 
many terms on signal a_to_g(3).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.numeric_std.ALL;
ENTITY calc is
  Port (Num1: in Signed (1 downto 0);
    Num2: in Signed (1 downto 0);
    S:  in STD_LOGIC_VECTOR (1 downto 0);
    a_to_g:out STD_LOGIC_VECTOR (6 downto 0));
end calc;

Architecture tris of calc is
signal SUM:Signed (4 downto 0);
signal RES:Signed (4 downto 0);
signal MUL:Signed (4 downto 0);
signal COM:Signed (4 downto 0);
signal DISP : signed(4 downto 0);
begin 
process(Num1,Num2,S)
  BEGIN
  CASE S IS
    WHEN "00"=>SUM<=resize(Num1,5)+Num2;
     WHEN "01"=>RES<=resize(Num1,5)-Num2;
    WHEN "10"=>
    if Num1>Num2 then 
    COM <= "11110";
    elsif Num1<Num2 then
    COM <= "11011";
    else
    COM <= "11010";
  end if;
    WHEN OTHERS=>MUL<=resize(Num1,3)*Num2;
    END CASE;
END PROCESS;
PROCESS (S,SUM,RES,MUL,COM)
BEGIN
IF (S="00") THEN DISP<=SUM;
ELSIF (S="01") THEN DISP<=RES;
ELSIF (S="10") THEN DISP<=COM;
ELSE DISP<=MUL;
  END IF;
    END PROCESS;  
      
process (DISP)
  begin
    case DISP is
  -- output numbers
  when "00000"=> a_to_g <="0000001";  --0
  when "00001"=> a_to_g <="1001111";  --1
  when "00010"=> a_to_g <="0010010";  --2
  when "00011"=> a_to_g <="0000110";  --3
  when "00100"=> a_to_g <="1001100";  --4
  when "00101"=> a_to_g <="0100100";  --5
  when "00110"=> a_to_g <="0100000";  --6
  when "00111"=> a_to_g <="0001101";  --7
  when "01000"=> a_to_g <="0000000";  --8
  when "01001"=> a_to_g <="0000100";  --9
  -- output symbols
  when "11010"=> a_to_g <="1000001";  --=
  when "11011"=> a_to_g <="1001110";  --<
  when "11110"=> a_to_g <="1111000";  -->
  when others => a_to_g <="0000000";
end case;
  end process;
end tris; 

Author: Lothar Miller (lkmiller) (Moderator)
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Yair Orta wrote:
> it says
WHO is IT?

> it says that logic equation has to many terms on signal a_to_g(3).
Nothing more? With wich words?

> USE IEEE.STD_LOGIC_UNSIGNED.ALL;
> USE IEEE.numeric_std.ALL;
Never ever use both of them together!
Use the numeric_std solely. It has all the conversions you need. Try 
this with Google translator, its German:
http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

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