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Forum: FPGA, VHDL & Verilog Traffic Light VHDL , counter


von Gabriel (Guest)


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Please some help with this code, I dont know where is the problem, is 
giving me these errors:


Error: Node instance "TLong" instantiates undefined entity "OneShot"
Error: Node instance "TShort" instantiates undefined entity "OneShot"

here is the code...
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity TimerCircuits is 
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port (LongTrig, ShortTrig, Clk: in std_logic;
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TS,TL : buffer std_logic);
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end entity TimerCircuits;
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architecture TimerBehavior of TimerCircuits is 
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component OneShot is 
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port (enable, Clk : in std_logic;
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    Duration : in integer range 0 to 25 ;
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    QOut : buffer std_logic );
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end component OneShot;
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signal SetCountLong, SetCountShort: integer range 0 to 25; 
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begin 
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SetCountLong <= 25;
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SetCountShort <=4;
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TLong:OneShot port map (enable=>LongTrig, Clk=>Clk, Duration=>SetCountLong, QOut=>TL);
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TShort:OneShot port map (enable=>ShortTrig, Clk=>Clk, Duration=>SetCountShort, QOut=>TS);
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end architecture TimerBehavior;

: Edited by Moderator
von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Gabriel wrote:
> here is the code...
It that all of the code?

> Error: Node instance "TLong" instantiates undefined entity "OneShot"
The entity "OneShot" is not known here in this module. You must 
implement an entity "OneShot" and include it in the build process.

> is giving me these errors:
What toolchain give you that error?

Next time try this:
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[vhdl]
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  VHDL code
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[/vhdl]

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