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Forum: FPGA, VHDL & Verilog HELP VHDL code for pipeline multiplier


Author: Blood Eagle (bloodeagle)
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Can somebody help me with VHDL code for a pipeline multiplier (10 & 8 
bits) ?
Thanks!

Author: TimGabelTeamG (Guest)
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Blood Eagle wrote:
> Can somebody help me with VHDL code for a pipeline multiplier (10
> & 8
> bits) ?
> Thanks!

c <= a * b;

Here ist your multiplier with one pipeline stage.

Author: Blood Eagle (bloodeagle)
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity tema is
generic (N2 : natural := 8 ;
         N1 : natural := 10  );
port(
        iRST    : in std_logic;
        iCLK    : in std_logic;
        iB      : in std_logic_vector(N2-1 downto 0);
        iA      : in std_logic_vector(N1-1 downto 0);
        iRez    : in std_logic_vector(N1+N2-2 downto 0);
        oRez    : out std_logic_vector(N1+N2-2 downto 0);
        oA      : out std_logic_vector(N1-1 downto 0);
        oB      : out std_logic_vector(N2-1 downto 0)
);
end tema;

architecture behave of tema is

signal sProd : std_logic_vector(N1-1 downto 0);
signal cZeros : std_logic_vector(N2-2 downto 0);
signal sProde : std_logic_vector(N1+N2-2 downto 0);

begin

cZeros <= (others => '0');

process(iA, iB)
begin
for i in 0 to N1-1 loop
    sProd(i) <= iB(N2-1) and iA(i);
end loop;
end process;

sProde <= cZeros & sProd;

process(iCLK, iRST)
begin
if iRST = '1' then
    oRez <= (others => '0');
    oA <= (others => '0');
    oB <= (others => '0');
elsif rising_edge(iCLK) then
   oRez <= Sprode + iRez(N1+N2-3 downto 0) & '0';
   oA <= iA;
   oB <= iB(N2-2 downto 0) & '0';
   end if;
end process;



end ;



I have this one ,but I don't know if it's right!

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