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Forum: FPGA, VHDL & Verilog Vhdl on FPGA, need to understand a syntax


Author: Hakon Veddegjerde (Company: Student) (patiknot)
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Hi!

I'm working on getting a single cycle arm processor to work on a FPGA 
chip.
but I have a problem with just one line to get it work.

I'm a beginner in vhdl and I'm just putting together prewritten 
code(from school).

here is my problem:

Y:  std_logic
A:  std_logic_vector(3 downto 0)
B:  std_logic
C:  std_logic

Y <= ((and A) and B) or C;

I dont understand what I'm anding A with. If I can get an understanding 
of the line, i can write a equivalent code to get it to work.

-Håkon

Author: .... (Guest)
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http://stackoverflow.com/questions/20296276/and-al...

2nd answer

it looks like something new in VHDL-2008

Author: Hakon Veddegjerde (Company: Student) (patiknot)
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thanks!

I solved my problem.

the solution was: Y<=((A(3) and A(2) and A(1) and A(0)) and B) or C

Author: Lothar Miller (lkmiller) (Moderator)
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You can kick away some of the brackets:
Y <= A(3) and A(2) and A(1) and A(0) and B   or  C;

: Edited by Moderator

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