Forum: FPGA, VHDL & Verilog Verilog Loop operation with registers.

Author: Eldar Ismailov (Company: Optimal Dynamics) (ismailov-e)
Posted on:

Rate this post
0 useful
not useful
Who can help me please.
I want to make some loop operation. for example: use loop in register 

reg [7:0] res;
reg [7:0] buff
for (i = 0; i < 8 ; i = i + 1)
res <= buff[i+1:i] + i;
module integers( clock, res
input clock;
output res;
wire clock;
reg [7:0] res;
reg [7:0] buff = 0;
genvar i;

  for (i = 0; i < 8 ; i = i + 1)
  always@ (negedge clock)
      res <= buff + i;
it outputs only one. but should counts.


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.